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S.E. Eldridge, C.D. Walter, "Hardware Implementation of Montgomery's Modular Multiplication Algorithm," IEEE Transactions on Computers, vol. 42, no. 6, pp. 693699, June, 1993.  
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@article{ 10.1109/12.277287, author = {S.E. Eldridge and C.D. Walter}, title = {Hardware Implementation of Montgomery's Modular Multiplication Algorithm}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {6}, issn = {00189340}, year = {1993}, pages = {693699}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.277287}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Hardware Implementation of Montgomery's Modular Multiplication Algorithm IS  6 SN  00189340 SP693 EP699 EPD  693699 A1  S.E. Eldridge, A1  C.D. Walter, PY  1993 KW  hardware implementation; Montgomery's modular multiplication; fast modular multiplication; digital arithmetic; multiplying circuits. VL  42 JA  IEEE Transactions on Computers ER   
Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.
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