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Hardware Implementation of Montgomery's Modular Multiplication Algorithm
June 1993 (vol. 42 no. 6)
pp. 693-699

Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.

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Index Terms:
hardware implementation; Montgomery's modular multiplication; fast modular multiplication; digital arithmetic; multiplying circuits.
Citation:
S.E. Eldridge, C.D. Walter, "Hardware Implementation of Montgomery's Modular Multiplication Algorithm," IEEE Transactions on Computers, vol. 42, no. 6, pp. 693-699, June 1993, doi:10.1109/12.277287
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