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Parallel Computations on Reconfigurable Meshes
June 1993 (vol. 42 no. 6)
pp. 678-692

The mesh with reconfigurable bus is presented as a model of computation. The reconfigurable mesh captures salient features from a variety of sources, including the CAAPP, CHiP, polymorphic-torus network, and bus automation. It consists of an array of processors interconnected by a reconfigurable bus system that can be used to dynamically obtain various interconnection patterns between the processors. A variety of fundamental data-movement operations for the reconfigurable mesh are introduced. Based on these operations, algorithms that are efficient for solving a variety of problems involving graphs and digitized images are also introduced. The algorithms are asymptotically superior to those previously obtained for the aforementioned reconfigurable architectures, as well as to those previously obtained for the mesh, the mesh with multiple broadcasting, the mesh with multiple buses, the mesh-of-trees, and the pyramid computer. The power of reconfigurability is illustrated by solving some problems, such as the exclusive OR, more efficiently on the reconfigurable mesh than is possible on the programmable random-access memory (PRAM).

[1] C. R. Dyer, "A VLSI pyramid machine for hierarchical parallel image processing," inProc. IEEE Conf. Pattern Recognition Image Processing, 1981.
[2] S. L. Tanimoto, "A pyramidal approach to parallel processing," inProc. Int. Symp. Comput. Architecture, June 1983, pp .
[3] R. Miller and Q. F. Stout, "Data movement techniques for the pyramid computer,"SIAM J. Comput., vol. 16, pp. 38-60, 1987.
[4] F. T. Leighton, "Parallel computations using mesh of trees," MIT, Cambridge, MA, Tech. Rep., 1982.
[5] D. Nath, F. N. Maheshwari, and P. C. P. Bhatt, "Efficient VLSI networks for parallel processing based on orthogonal trees,"IEEE Trans. Comput., 1983.
[6] Q. F. Stout, "Mesh connected computers with broadcasting,"IEEE Trans. Comput., vol. C-32, pp. 826-830, 1983.
[7] S. H. Bokhari, Finding maximum on an array processor with a global bus,IEEE Trans. Comput., vol. C-33, no. 2, pp. 133-139, Feb. 1984.
[8] V. K. Prasanna-Kumar and C. S. Raghavendra, "Array processor with multiple broadcasting," inProc. Annu. Symp. Computer Architecture, June 1985.
[9] Q. F. Stout, "Meshes with multiple buses," inProc. 27th IEEE Symp. Foundations Comput. Sci., 1986, pp. 264-273.
[10] Hunt, "The ICL DAP and its application to image processing," inLanguages and Architectures for Image Processing, M. J. B. Duff and S. Levialdi, Eds. New York/London: Academic Press, 1981.
[11] L. Snyder, "Introduction to the configurable highly parallel computer,"Comput., vol. 15, no. 1, pp. 47-56, Jan. 1982.
[12] A. Aggarwal, "Optimal bounds for finding maximum on array of processors withkglobal buses,"IEEE Trans. Comput., vol. C-35, no. 1, pp. 62-64, Jan. 1986.
[13] D. M. Champion and J. Rothstein, "Immediate parallel solution of the longest common subsequence problem," inProc. Int. Conf. Parallel Processing, Aug. 1987, pp. 70-77.
[14] H. Li and M. Maresca, "Polymorphic-torus network,"IEEE Trans. Comput., vol. 38, no. 9, pp. 1345-1351, Sept. 1989.
[15] J. D. Ullman,Computational Aspects of VLSI. New York: Computer Science Press, 1984.
[16] V. K. Prasanna-Kumar and D. Reisis, "Parallel image processing on enhanced arrays," inProc. Int. Conf. Parallel Processing, Aug. 1987, pp. 909-912.
[17] M. Furst, J. Saxe, and M. Sipser, "Parity, circuits and polynomial time hierarchy," inProc. IEEE Symp. Found. Comput. Sci., Oct. 1981, pp. 260-270.
[18] L. G. Valiant, "Parallelism in comparison problems,"SIAM J. Comput., vol. 3, 1975.
[19] R. E. Ladner and M. J. Fischer, "Parallel prefix computation,"J. ACM, vol. 27, no. 4, pp. 831-838, Oct. 1980.
[20] D. Nassimi and S. Sahni, "Data broadcasting in SIMD computers,"IEEE Trans. Comput., vol. C-30, no. 2, pp. 101-107, Feb. 1981.
[21] V. K. Prasanna-Kumar and D. Reisis, "VLSI arrays with reconfigurable buses," Comput. Res. Inst., Univ. Southern CA, Los Angeles, Tech. Report CRI-87-48, Sept. 1987.
[22] R. Miller and Q. F. Stout, "Some graph and image processing algorithms for the hypercube," inProc. SIAM Conf. Hypercube Multiprocessor, 1987.
[23] Q. F. Stout, "Pyramid computer algorithms optimal for the worst-case," inParallel Computer Vision, L. Uhr, Ed. New York: Academic Press, 1987, pp. 147-168.
[24] Y. Shiloach and U. Vishkin, "AO(logN) parallel connectivity algorithm,"J. Algorithms, vol. 3, 1982.
[25] D. S. Hirschberg, A. K. Chandra, and D. V. Sarwate, "Computing connected components on parallel computers,"Commun. Assoc. Comput. Mach., pp. 461-464, 1979.
[26] S. E. Hambrusch and J. Simon, "Solving undirected graph problems on VLSI," Dept. Comput. Sci., PA State Univ., Univ. Park, PA, Tech. Rep. CS-81-23, 1981.
[27] C. Savage and J. Ja'Ja', "Fast, efficient parallel algorithms for some graph problems,"SIAM J. Comput., vol. 10, pp. 682-691, 1981.
[28] M. Atallah and R. Kosaraju, "Graph problems on a mesh connected processor array,"J. Assoc. Comp. Mach., vol. 31, pp. 649-667, 1983.
[29] J. G. Nash and D. B. Shu, "The image understanding architecture," inProc. 21st Annu. Asilomar Conf. Signals, Syst., Comput.(Monterey, CA), Nov. 1987.
[30] C. C. Weemset al., "The image understanding architecture,"Int. J. Comput. Vision, vol. 2, pp. 251-282, 1989.
[31] H. Freeman and R. Shapira, "Determining the minimal-area enclosing rectangle for an arbitrary closed curve,"Commun. Assoc. Comput. Mach., vol. 18, pp. 409-413, 1975.
[32] V. K. Prasanna-Kumar and M. Eshaghian, "Parallel geometric algorithms for digitized pictures on mesh of trees organization," inProc. Int. Conf. Parallel Processing, Aug. 1986, pp. 270-273.
[33] H. M. Alnuweiri and V. K. Prasanna-Kumar, "Parallel architectures and algorithms for image component labeling," Inst. Robotics Intell. Syst., Tech. Rep. IRIS #253, May 1989.
[34] J. Ja'Ja' and V. K. Prasanna Kumar, "Information transfer in distributed computing with applications to VLSI,"J. ACM, Jan. 1984.
[35] J. Ja'Ja', V. K. Prasanna-Kumar and J. Simon, "Information transfer under different sets of protocols,"SIAM J. Comput., vol. 13, no. 4, pp. 840-849, Nov. 1984.
[36] J.-W. Jang and V. K. Prasanna, "An optimal sorting algorithm on reconfigurable mesh," Inst. Robotics Intell. Syst., Tech. Rep. IRIS#277, Aug. 1991.
[37] J-W. Jang, H. Park and V. K. Prasanna, "A fast algorithm for computing histogram on reconfigurable mesh," Inst. Robotics Intell. Syst., Tech. Rep. IRIS#290, Feb. 1992.
[38] J.-W. Jang, H. Park, and V. K. Prasanna, "An optimal multiplication algorithm on reconfigurable mesh," Inst. Robotics Intell. Syst., Tech. Rep. IRIS#294, Mar. 1992.
[39] D. Reisis, "An efficient convex hull computation on the reconfigurable mesh," inProc. Int. Parallel Processing Symp., 1992, pp. 142-145.
[40] Y. Ben-Asher, D. Peleg, R. Ramaswami, and A. Schuster, "The power of reconfiguration,"J. Parallel Distributed Computing, pp. 139-153, 1991.
[41] J. Jenq and S. Sahni, "Reconfigurable mesh algorithms for the area and perimeter of image components and histogramming," inProc. Int. Conf. Parallel Processing, 1991, pp. 280-281.
[42] J. Jenq and S. Sahni, "Reconfigurable mesh algorithms for image shrinking, expanding, clustering, and template matching," inProc. Int. Parallel Processing Symp., 1991, pp. 208-215.
[43] K. Nakano, T. Masuzawa, and N. Tokura, "A sub-logarithmic time sorting algorithm on a reconfigurable mesh,"IEICE Trans., vol. E74, no. 11, pp. 3894-3901, Nov. 1991.
[44] B. F. Wang, G. H. Chen, and F. C. Lin, "Constant time sorting on a processor array with a reconfigurable bus systems,"Info. Processing Letts., pp. 187-192, 1990.
[45] M. M. Eshaghian and V. K. Prasanna-Kumar, "VLSI electro-optical computers for signal and image processing," inProc. 3rd Int. Conf. Supercomputing, 1988.
[46] R. Miller, V. K. Prasanna Kumar, D. Reisis, and Q. F. Stout, "Meshes with reconfigurable buses," inProc. 5th MIT Conf. Advanced Res. VLSI(Cambridge, MA), 1988, pp. 163-178.
[47] R. Miller and Q. F. Stout, "Geometric algorithms for digitized pictures on a mesh-connected computer,"IEEE Trans. Pattern Analysis Mach. Intell., vol. PAMI-7, pp. 216-228, 1985.
[48] D. Reisis and V. K. Prasanna Kumar, "VLSI arrays with reconfigurable buses," inProc. Int. Conf. Supercomput.(Athens, Greece), June 1987.
[49] S. Olariu, J. Schwoing, and J. Zhang, "Fast Computer Vision Algorithms for Reconfigurable Meshes," in Proc. Int. Parallel Processing Symp., Mar. 1992, pp. 258-261.

Index Terms:
parallel algorithms, complexity; reconfigurable meshes; model of computation; reconfigurable architectures; reconfigurability; PRAM; computational complexity; multiprocessor interconnection networks; parallel algorithms.
Citation:
R. Miller, V.K. Prasanna-Kumar, D.I. Reisis, Q.F Stout, "Parallel Computations on Reconfigurable Meshes," IEEE Transactions on Computers, vol. 42, no. 6, pp. 678-692, June 1993, doi:10.1109/12.277290
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