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Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application
April 1993 (vol. 42 no. 4)
pp. 494-497

Two exponentiation circuits are proposed. Using the fact that squaring is a linear operation over GF(2/sup n/), a time-space tradeoff in smartcard-based circuitry is presented. It is shown how multiplication is performed by a single shift, based on replacing the public key alpha /sup a/ in GF(2/sup n/) by its minimal polynomial. Other considerations, related to structure regularity and the possible use of dynamic shift registers, are also treated.

[1] W. Diffie and M. Hellman, "New directions in cryptography,"IEEE Trans. Inform. Theory, vol. IT-22, pp. 644-654, 1976.
[2] T. Elgamal, "A Public-Key Cryptosystem and a Signature Scheme Based on Discrete Logarithms,"IEEE Trans. Information Theory, Vol. IT-31, 1985, pp, 469-472.
[3] T. Bethet al., "Architectures for exponentiation in GF(2n)," inAdvances in Cryptology--CRYPTO '86, LNCS 263, pp. 302-310.
[4] T. Beth and D. Gollman, "Algorithm engineering for public key algorithms,"IEEE J. Select. Areas Commun., vol. SAC-7, pp. 458-466, 1989.
[5] P. A. Scottet al., "Architectures for exponentiation in GF(2m),"IEEE J. Select. Areas Commun., vol. SAC-6, pp. 578-586, 1988.
[6] C.C. Wang and D. Pei, "A VLSI design for computing exponentiations in GF(2m) and its application to generate pseudorandom number sequences,"IEEE Trans. Comput., vol. 39, pp. 258-262, 1990.
[7] G.B. Agnewet al., "Fast exponentiation in GF(2n)," inAdvances in Cryptology-EUROCRYPT '88, LNCS 330, pp. 251-256.
[8] J. J. Quisquater and M. De Soete, "Speeding up smartcard RSA computations with insecure coprocessors," inProc. SMART CARD 2000, Amsterdam, Oct. 1989.
[9] S. Kawamura and A. Shimbo, "Performance analysis of server-aided secret computation protocols for the RSA cryptosystem,"Trans. IEICE, vol. E73, pp. 1073-1080, 1990.
[10] W. W. Peterson and E. J. Weldon,Error-Correcting Codes, 2nd ed. Cambridge, MA: M.I.T. Press, 1972.
[11] J.L. Massey and J.K. Omura, "Computational method and apparatus for finite field arithmetic," U.S. Patent 4587627.
[12] C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, "VLSI architecture for computing multiplications and inverses in GF(2m),"IEEE Trans. Comput., vol. C-34, pp. 709-716, Aug. 1985.
[13] B. Arazi, "Connection between primitive generators of GF(2n),"Electron. Lett., vol. 16, pp. 223-225, 1980.
[14] J.A. Gordon, "Very simple method to find the minimal polynomial of an arbitrary nonzero element of a finite field,"Electron. Lett., vol. 12, pp. 663-664, 1976.

Index Terms:
exponentiation circuits; linear operation; time-space tradeoff; smartcard-based circuitry; public key; structure regularity; dynamic shift registers; cryptography; digital arithmetic; smart cards.
B. Arazi, "Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application," IEEE Transactions on Computers, vol. 42, no. 4, pp. 494-497, April 1993, doi:10.1109/12.214694
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