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Issue No.04 - April (1993 vol.42)
pp: 458-470
ABSTRACT
<p>A directory of state information is introduced into a multistage interconnection network (MIN) switch, and a multiple copy cache coherence protocol is developed. It is shown that the protocol is better than a single copy protocol on this MIN with directories (MIND) scheme. A network called the multistage bus network (MBN), which introduces a bus and multiple snoopers into the switches of a MIN, is presented. The snooping buses form multiple trees with the memories at the roots and the processors at the leaves. Each switch contains directories to hold state information on the shared blocks that is used to filter the coherence traffic from one level to another. The shared requests pass through the directories, whereas the private requests pass directly from the bus in one level to the bus in the next level. Analytical and simulation models for these multistage cache coherent architectures are developed. Both the MIND and the MBN schemes are studied with a simple multiple copy protocol. The results show that the MBN scheme performs better than the MIND or conventional scheme.</p>
INDEX TERMS
cache coherent multistage interconnection networks; multiple copy cache coherence protocol; multistage bus network; coherence traffic; simulation models; multiprocessor interconnection networks; performance evaluation; protocols.
CITATION
A.K. Nanda, L.N. Bhuyan, "Design and Analysis of Cache Coherent Multistage Interconnection Networks", IEEE Transactions on Computers, vol.42, no. 4, pp. 458-470, April 1993, doi:10.1109/12.214692
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