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| E.D. Di Claudio, G. Orlandi, F. Piazza, "A Systolic Redundant Residue Arithmetic Error Correction Circuit," IEEE Transactions on Computers, vol. 42, no. 4, pp. 427-432, April, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/12.214689, author = {E.D. Di Claudio and G. Orlandi and F. Piazza}, title = {A Systolic Redundant Residue Arithmetic Error Correction Circuit}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {4}, issn = {0018-9340}, year = {1993}, pages = {427-432}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.214689}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Systolic Redundant Residue Arithmetic Error Correction Circuit IS - 4 SN - 0018-9340 SP427 EP432 EPD - 427-432 A1 - E.D. Di Claudio, A1 - G. Orlandi, A1 - F. Piazza, PY - 1993 KW - error recovery; processing element; residue arithmetic; systolic redundant residue arithmetic error correction circuit; concurrent fault tolerance capability; real-time applications; transient errors; memory element; redundant residue number system; decision table; high speed VLSI circuit realization; parallel systolic architecture; digital arithmetic; error correction; parallel algorithms; systolic arrays; VLSI. VL - 42 JA - IEEE Transactions on Computers ER - | |||
In highly integrated processors, a concurrent fault tolerance capability is particularly important, especially for real-time applications. In fact, in these systems, transient errors are often present, but are difficult to correct online. Error recovery procedures applied for each processing or memory element require large amount of hardware and can reduce throughput. Residue arithmetic has intrinsic fault tolerance capability and requires less complex hardware. A single error correction procedure based on the use of a redundant residue number system (RRNS) and the base extension operation is proposed. The method uses a very small decision table and works in parallel mode; therefore it is suitable for high speed VLSI circuit realization. A parallel systolic architecture which realizes the algorithm is introduced.
[1] F. J. Taylor, "Residue arithmetic: A tutorial with examples,"IEEE Comput. Mag., pp. 50-62, May 1984.
[2] N. S. Szabo and R. I. Tanaka,Residue Arithmetic and its Application to Computer Technology. New York, McGraw-Hill, 1967.
[3] R. W. Watson and C. W. Hastings, "Self-checked computation using residue arithmetic,"Proc. IEEE, vol. 54, pp. 1920-1931, Dec. 1966.
[4] D. Mandelbaum, "Error correction in residue arithmetic,"IEEE Trans. Comput., vol. C-21, pp. 538-545, June 1972.
[5] S. S. Yau and Y. C. Liu, "Error correction in redundant residue number systems,"IEEE Trans. Comput., vol. C-22, pp. 5-11, Jan. 1973.
[6] H. L. Garner, "Error checking and the structure of binary addition," Ph.D. dissertation, Univ. Michigan, Ann Arbor, MI, 1958.
[7] P. W. Cheney, "An investigation of residue number systems for digital systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1962.
[8] F. Barsi and P. Maestrini, "Error correcting properties of redundant residue number systems,"IEEE Trans. Comput., vol. C-22, pp. 307-315, Mar. 1973.
[9] V. Ramachandran, "Single error correction in residue number systems,"IEEE Trans. Comput., vol. C-32, pp. 504-507, May 1983.
[10] M. H. Etzel and W. K. Jenkins, "Redundant residue number systems for error detection and correction in digital filters,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-28, pp. 538-544, Oct. 1980.
[11] W. K. Jenkins, "The design of error checkers for self-checking residue number arithmetic,"IEEE Trans. Comput., vol. C-32, pp. 388-396, Apr. 1983.
[12] R. Wilmhoff and F. J. Taylor, "On hard errors in RNS architectures,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 772-774, June 1983.
[13] J. J. Stone, "Multiple burst correction with the Chinese Remainder Theorem,"J. SIAM, vol. 11, no. 1, pp. 74-81, Mar. 1963.
[14] R. J. Cosentino, "Fault tolerance in a systolic residue arithmetic processor array,"IEEE Trans. Comput., vol. 37, no. 7, pp. 886-890, July 1988.
[15] A. P. Shenoy and R. Kumaresan, "Fast base extension using a redundant modulus in RNS,"IEEE Trans. Comput., vol. 38, no. 2, Feb. 1989.
[16] E. D. Di Claudio, G. Orlandi, and F. Piazza, "A fast binary arithmetic implementation of RNS DSP processors," inProc. IEEE Int. Symp. Circuits Syst., vol. 1, pp. 2120-2123, May 1990.