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A Systolic Redundant Residue Arithmetic Error Correction Circuit
April 1993 (vol. 42 no. 4)
pp. 427-432

In highly integrated processors, a concurrent fault tolerance capability is particularly important, especially for real-time applications. In fact, in these systems, transient errors are often present, but are difficult to correct online. Error recovery procedures applied for each processing or memory element require large amount of hardware and can reduce throughput. Residue arithmetic has intrinsic fault tolerance capability and requires less complex hardware. A single error correction procedure based on the use of a redundant residue number system (RRNS) and the base extension operation is proposed. The method uses a very small decision table and works in parallel mode; therefore it is suitable for high speed VLSI circuit realization. A parallel systolic architecture which realizes the algorithm is introduced.

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Index Terms:
error recovery; processing element; residue arithmetic; systolic redundant residue arithmetic error correction circuit; concurrent fault tolerance capability; real-time applications; transient errors; memory element; redundant residue number system; decision table; high speed VLSI circuit realization; parallel systolic architecture; digital arithmetic; error correction; parallel algorithms; systolic arrays; VLSI.
Citation:
E.D. Di Claudio, G. Orlandi, F. Piazza, "A Systolic Redundant Residue Arithmetic Error Correction Circuit," IEEE Transactions on Computers, vol. 42, no. 4, pp. 427-432, April 1993, doi:10.1109/12.214689
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