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Systematic Design of Pipelined Recursive Filters
April 1993 (vol. 42 no. 4)
pp. 413-426

Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required.

[1] K. K. Parhi and D. G. Messerschmitt, "Pipelined VLSI recursive filter architectures using scattered look-ahead and decomposition," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, Apr. 1988, pp. 2120-2123.
[2] K. K. Parhi and M. Hatamian, "A high sample rate recursive digital filter chip," inVLSI Signal Processing III, New York, IEEE Press, 1988, ch. 1.
[3] K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters-Parts I and II,"IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, no. 7, pp. 1099-1135, July 1989.
[4] S. C. Knowles, J. G. MacWhirter, R. F. Woods, and J. V. MacCanny, "Bit-level systolic architectures for high performance IIR filtering,"J. VLSI Signal Processing, vol. 1, no. 1, pp. 9-24, Feb. 24, 1989.
[5] O. C. MacNally, J. V. MacCanny, and R. F. Woods, "Optimised bit level architectures for IIR filtering," inProc. IEEE Int. Conf. Comput. Design: VLSI Comput. Processors, ICCD-90, Cambridge, MA, Sept. 17-19, 1990, pp. 302-306.
[6] O. C. MacNally, W. P. Marane, and J. V. MacCanny, "Design and test of a bit parallel 2nd order IIR filter structure," inProc. IEEE Int. Conf. Acoust, Speech, Signal Processing, ICASSP-91, Toronto, Canada, May 14-17, 1991, pp. 1189-1192.
[7] O. C. MacNally, J. V. MacCanny, and R. F. Woods, "A 40 megasample IIR filter chip," inProc. Int. Conf. ASAP, Costa Brava, Spain, Sept. 2-4, 1991.
[8] A. Avizienis, "Signed-digit number representations for fast parallel arithmetic,"IRE Trans. Electron. Comput., vol. 10, pp. 389-400, Sept. 1961.
[9] M. Lapointe and H. T. Huynh, "Algorithme de l'accumulateur," inProc. Canadian Conf. Elect. Comput. Eng, Montreal, Canada, Sept. 17-20, 1989, pp. 185-190 (in French).
[10] M. Lapointe, P. Fortier, and H. T. Huynh, "A new faster and simpler systolic structure for IIR filters," inProc. IEEE Int. Symp. Circuits Syst., New Orleans, LA, May 1-3, 1990, pp 1227-1230.
[11] M. Lapointe, "Architecture concurrente et applicationsàdes réalisations rapides de filtres numériques invariants et adaptatifs," Ph.D. dissertation, Elect. Eng. Dept., Laval Univ., Nov. 1990 (in French).
[12] A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, and P. G. A. Jespers, "A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor,"IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 748-756, June 1990.
[13] H. R. Srinivas and K. K. Parhi, "High-speed VLSI arithmetic processor architectures using hybrid number representation," inProc. IEEE Int. Conf. Comput. Design, Cambridge, MA, Oct. 14-16, 1991.
[14] H. R. Srinivas and K. K. Parhi, "A fast VLSI adder architecture,"IEEE J. Solid-State Circuits, vol. 27, May 1992.
[15] M. D. Ercegovac and T. Lang, "On-the-fly conversion of redundant into conventional representations,"IEEE Trans. Comput., vol. C-36, no. 7, pp. 895-897, July 1987.
[16] P. M. Ebert, J. E. Mazo, and M. G. Taylor, "Overflow oscillations in digital filters,"Bell Syst. Tech. J., pp. 2999-3020, Nov. 1969.
[17] K. S. Trivedi and M. D. Ercegovac, "On-line algorithms for division and multiplication,"IEEE Trans. Comput., vol. 26, no. 7, pp. 681-687, July 1977.
[18] S. A. White, "Applications of distributed arithmetic to digital signal processing: A tutorial review,"IEEE ASSP Mag., vol. 6, no. 3, pp. 4-19, July 1989.
[19] M. Lapointe, P. Fortier, and H. T. Huynh, "Fast parallel realization of the LMS algorithm in O(log N) computation time," inProc. 15th Biennial Symp. Commun., Kingston, Ont., Canada, June 3-6, 1990, pp. 45-48.
[20] M. Lapointe, P. Fortier, and H. T. Huynh, "A very fast digital realization of a time-domain block LMS filter," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, ICASSP-91, Toronto, Canada, May 14-17, 1991, pp. 2101-2104.
[21] M. Lapointe, H. T. Huynh, and P. Fortier, "Architecture hautement concurrente de l'algorithme des moindres carrés moyens,"Canadian J. Elect. Comput. Eng., vol. 16, no. 3, pp. 93-104, 1991 (in French).
[22] N. Weste and K. Eshraghian,Principles of CMOS Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1985, pp. 322-325.

Index Terms:
systematic design; pipelined recursive filters; multiplication algorithm; most significant digit first; multiplier; pipelining delays; minimum hardware; minimum latency; number system radix; second-order all-pole filter; radix-4 representation; delays; digital arithmetic; digital filters; pipeline processing.
Citation:
M. Lapointe, H.T. Huynh, P. Fortier, "Systematic Design of Pipelined Recursive Filters," IEEE Transactions on Computers, vol. 42, no. 4, pp. 413-426, April 1993, doi:10.1109/12.214688
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