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Issue No.04 - April (1993 vol.42)
pp: 396-412
ABSTRACT
<p>A branch target buffer (BTB) can reduce the performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. Two major issues in the design of BTBs that achieves maximum performance with a limited number of bits allocated to the BTB implementation are discussed. The first is BTB management. A method for discarding branches from the BTB is examined. This method discards the branch with the smallest expected value for improving performance; it outperforms the least recently used (LRU) strategy by a small margin, at the cost of additional complexity. The second issue is the question of what information to store in the BTB. A BTB entry can consist of one or more of the following: branch tag, prediction information, the branch target address, and instructions at the branch target. Various BTB designs, with one or more of these fields, are evaluated and compared.</p>
INDEX TERMS
branch target buffer design; optimization; performance penalty; branches; pipelined processors; caching; least recently used; complexity; branch tag; prediction information; branch target address; instructions; buffer storage; instruction sets; pipeline processing.
CITATION
C.H. Perleberg, A.J. Smith, "Branch Target Buffer Design and Optimization", IEEE Transactions on Computers, vol.42, no. 4, pp. 396-412, April 1993, doi:10.1109/12.214687
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