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| C.D. Walter, "Systolic Modular Multiplication," IEEE Transactions on Computers, vol. 42, no. 3, pp. 376-378, March, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/12.210181, author = {C.D. Walter}, title = {Systolic Modular Multiplication}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {3}, issn = {0018-9340}, year = {1993}, pages = {376-378}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.210181}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Systolic Modular Multiplication IS - 3 SN - 0018-9340 SP376 EP378 EPD - 376-378 A1 - C.D. Walter, PY - 1993 KW - systolic array; modular multiplication; clock cycle; latency; multiplicands; RSA cryptosystems; digital arithmetic; multiplying circuits; systolic arrays. VL - 42 JA - IEEE Transactions on Computers ER - | |||
A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.
[1] E. F. Brickell, "A fast modular multiplication algorithm with application to two-key cryptography," inAdvances in Cryptology--Proc. of CRYPTO 82, Chaumet al., Eds. New York: Plenum, 1983, pp. 51-60.
[2] S. E. Eldridge, "A faster modular multiplication algorithm,"Intern. J. Comput. Math., vol. 40, pp. 63-68, 1991.
[3] S. E. Eldridge and C. D. Walter, "Hardware implementation of Montgomery's modular multiplication algorithm,"IEEE Trans. Comput., to be published.
[4] Ç. K. Koçand C. Y. Hung, "Bit-level systolic arrays for modular multiplication,"J. VLSI Signal Processing, vol. 3, pp. 215-223, 1991.
[5] J. V. McCanny and J. G. McWhirter, "Implementation of signal processing functions using 1-bit systolic arrays,"Electron. Lett., vol. 18, pp. 241-243, 1982.
[6] P. L. Montgomery, "Modular multiplication without trial division,"Mathemat. of Computat., vol. 44, pp. 519-521, 1985.
[7] R.L. Rivest, A. Shamir, and L. Adleman, "A Method for Obtaining Digital Signatures and Public-Key Cryptosystems,"Comm. ACM, Vol. 21, No. 2, Feb. 1978, pp. 120-126.
[8] M. Shand, P. Bertin, and J. Vuillemin, "Hardware speedups in long integer multiplication,"ACM Sigarch, vol. 19, pp. 106-113, 1991.