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C.D. Walter, "Systolic Modular Multiplication," IEEE Transactions on Computers, vol. 42, no. 3, pp. 376378, March, 1993.  
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@article{ 10.1109/12.210181, author = {C.D. Walter}, title = {Systolic Modular Multiplication}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {3}, issn = {00189340}, year = {1993}, pages = {376378}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.210181}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Systolic Modular Multiplication IS  3 SN  00189340 SP376 EP378 EPD  376378 A1  C.D. Walter, PY  1993 KW  systolic array; modular multiplication; clock cycle; latency; multiplicands; RSA cryptosystems; digital arithmetic; multiplying circuits; systolic arrays. VL  42 JA  IEEE Transactions on Computers ER   
A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.
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