Issue No.03 - March (1993 vol.42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.210181
<p>A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.</p>
systolic array; modular multiplication; clock cycle; latency; multiplicands; RSA cryptosystems; digital arithmetic; multiplying circuits; systolic arrays.
C.D. Walter, "Systolic Modular Multiplication", IEEE Transactions on Computers, vol.42, no. 3, pp. 376-378, March 1993, doi:10.1109/12.210181