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Systolic Modular Multiplication
March 1993 (vol. 42 no. 3)
pp. 376-378

A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.

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Index Terms:
systolic array; modular multiplication; clock cycle; latency; multiplicands; RSA cryptosystems; digital arithmetic; multiplying circuits; systolic arrays.
Citation:
C.D. Walter, "Systolic Modular Multiplication," IEEE Transactions on Computers, vol. 42, no. 3, pp. 376-378, March 1993, doi:10.1109/12.210181
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