Issue No.03 - March (1993 vol.42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.210168
<p>The authors investigate how much cache miss ratios increase when blocks are disabled. It is shown how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, an efficient approach is developed for calculating the exact distribution of miss ratio increases from all fault patterns, and this approach is applied to the ATUM traces. Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size and is negligible (>2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled.</p>
performance implications; cache faults; fault patterns; ATUM traces; buffer storage; fault tolerant computing; performance evaluation.
A.F. Pour, "Performance Implications of Tolerating Cache Faults", IEEE Transactions on Computers, vol.42, no. 3, pp. 257-267, March 1993, doi:10.1109/12.210168