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Issue No.02 - February (1993 vol.42)
pp: 228-234
<p>Many results regarding the probability of aliasing for multiple-input compactors have been derived under error assumptions that are not very realistic for VLSI circuits. Recently, the value of aliasing probability has been proven to tend to 2/sup -k/, where k is the number of binary memory elements of the linear compactor. This result is based on the assumption that the compactor is characterized by an irreducible polynomial and that the 'no error' vector has a probability different from zero. In these notes, the above result is generalized. More specifically, it is proved that it is valid if any two error vectors, neither of which needs to be the 'no error' vector, have probabilities of occurrence different from zero. To make the error model complete, the situation in which exactly one error vector has a probability different from zero is also considered. For the latter type of error distributions, the test lengths at which aliasing occurs are determined. Simple proofs for the results are provided; they are based on standard linear algebra notions and well-known theorems.</p>
multiple input signature analysis; probability; multiple-input compactors; error assumptions; VLSI circuits; binary memory elements; irreducible polynomial; error model; aliasing; standard linear algebra notions; built-in self test; feedback; logic testing; shift registers.
T. Kameda, S. Pilarski, A. Ivanov, "Notes on Multiple Input Signature Analysis", IEEE Transactions on Computers, vol.42, no. 2, pp. 228-234, February 1993, doi:10.1109/12.204795
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