This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Notes on Multiple Input Signature Analysis
February 1993 (vol. 42 no. 2)
pp. 228-234

Many results regarding the probability of aliasing for multiple-input compactors have been derived under error assumptions that are not very realistic for VLSI circuits. Recently, the value of aliasing probability has been proven to tend to 2/sup -k/, where k is the number of binary memory elements of the linear compactor. This result is based on the assumption that the compactor is characterized by an irreducible polynomial and that the 'no error' vector has a probability different from zero. In these notes, the above result is generalized. More specifically, it is proved that it is valid if any two error vectors, neither of which needs to be the 'no error' vector, have probabilities of occurrence different from zero. To make the error model complete, the situation in which exactly one error vector has a probability different from zero is also considered. For the latter type of error distributions, the test lengths at which aliasing occurs are determined. Simple proofs for the results are provided; they are based on standard linear algebra notions and well-known theorems.

[1] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.
[2] G. Birkhoff and S. MacLane,A Survey of Modern Algebra, 3rd ed. New York: Macmillan, 1965.
[3] W. C. Carter, "The ubiquitous parity bit," inProc. FTCS-12, June 1982, pp. 289-296.
[4] W. Daehn, T. W. Williams, and K. D. Wagner, "Aliasing errors in linear automata used as multiple-input signature analyzers,"IBM J. Res. Develop., vol. 34, no. 2/3, pp. 363-380, Mar./May 1990.
[5] M. Damiani, P. Olivo, M. Favalli, S. Ercolani, and B. Riccò, "Aliasing errors in signature analysis testing with multiple-input shift-registers," inProc. IEEE Euro. Test Conf., Apr. 1989, pp. 346-353.
[6] M. Damiani, P. Olivo, and B. Riccó, "Analysis and design of linear finite state machines for signature analysis testing,"IEEE Trans. Comput., vol. 40, no. 9, pp. 1034-1045, Sept. 1991.
[7] R. David, "Comments on 'Signature analysis for multiple output circuits,"IEEE Trans. Comput., vol. 39, no. 2, pp. 287-288, Feb. 1990.
[8] W. Feller,An Introduction to Probability Theory and Its Applications, Vol. 1, New York: Wiley, 1950.
[9] R. A. Frohwerk, "Signature analysis: A new digital field service method,"Hewlett-Packard J., pp. 2-8, May 1977.
[10] H. Fujiwara,Logic Testing and Design for Testability. Cambridge, MA: MIT Press, 1985.
[11] S. Z. Hassan, D. J. Lu, and E. J. McCluskey, "Parallel signature analyzers--Detection capability and extensions," inProc. 26th IEEE Comput. Society Int. Conf., COMPCON Spring 83, Feb.-Mar. 1983, pp. 440-445.
[12] J. P. Hayes, "Check sum test methods," inProc. FTCS-6, June 1976, pp. 114-119.
[13] A. Hlawiczka, "Hybrid design of parallel signature analyzers," inProc. IEEE Euro. Test Conf., Apr 1989, pp. 346-360.
[14] P. D. Hortensius, R. D. Mcleod, W. Pries, D. M. Miller, and H. C. Card, "Cellular automata based pseudorandom number generators for built-in self-test,"IEEE Trans. Comput.-Aided Design, vol. 8, no 8, pp. 842-59, Aug. 1989.
[15] K. Iwasaki and F. Arakawa, "An analysis of the aliasing probability of multiple input signature registers in the case of a 2m-ary symmetric channel,"IEEE Trans. Comput.-Aided Design, vol. 9, no. 4, pp. 427-438, Apr. 1990.
[16] E. J. McCluskey,Logic Design Principles: with Emphasis on Testable Semi-Custom Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1986, pp. 448-450.
[17] C.C. McDuffee,Vectors and Matrices. Ithaca, NY: Math. Assoc. of America, 1961.
[18] D. M. Miller and S. Zhang, "Aliasing in multiple-input data compactors," inProc. Canadian Conf. Elect. and Comput. Eng., Sept. 1989, pp. 347-351.
[19] J. C. Muzio, F. Ruskey, R. C. Aitken, and M. Serra, "Aliasing probabilities for some data compression techniques,"Developments in IC Testing, D. M. Miller, Ed. London, England: Academic, 1987.
[20] W. Nef,Linear Algebra. New York: Dover, 1988.
[21] K. P. Parker, "Compact testing: Testing with compressed data," inProc. FTCS-6, June 1976, pp. 93-98.
[22] W. W. Peterson and E. J. Weldon,Error-Correcting Codes. Cambridge MA: M.I.T. Press, 1972.
[23] D. K. Pradhan, S. K. Gupta, and M. G. Karpovsky, "Aliasing probability for multiple input signature analyzer,"IEEE Trans. Comput., vol. 39, no. 4, pp. 586-592, Apr. 1990.
[24] J. P. Robinson and N. R. Saxena, "Simultaneous signature and syndrome compression,"IEEE Trans. Comput.-Aided Design, vol. 7, no. 5, pp. 584-589, May 1988.
[25] T. Sridhar, D. S. Ho, T. J. Powell, and S. M. Thatte, "Analysis and simulation of parallel signature analyzers," inProc. Int. Test Conf., Philadelphia, PA, Nov. 1982, pp. 656-661.
[26] G. Strang,Linear Algebra and Its Applications, 3rd ed. San Diego, CA: Harcourt Brace Jovanovich, 1988.
[27] L.-T. Wang and E. J. McCluskey, "Hybrid designs generating maximum-length sequences,"IEEE Trans. Comput.-Aided Design, vol. 7, pp. 91-99, Jan. 1988.
[28] T. W. Williams and W. Daehn, "Aliasing probability for multiple-input signature analyzers with dependent inputs," inProc. IEEE COMPEURO, May 1989, pp. 120-127.
[29] T. W. Williams and W. Daehn, "Aliasing errors in multiple-input signature analysis registers," inProc. IEEE Int. Test Conf., Apr. 1989, pp. 338-345.
[30] T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, "Comparison of aliasing errors for primitive and non-primitive Polynomials," inProc. ITC, Sept. 1986, pp. 282-288.
[31] Y. Zorian and V. K. Agarwal, "A general scheme to optimize error masking in built-in self-testing," inProc. FTCS-16, July 1986, pp. 410-415.
[32] Proposed IEEE P1149.1 Standard Test Access Port and Boundary-Scan Architecture, Draft D3, Jan. 18, 1989.
[33] "The challenges of self-test,"IEEE Design&Test Mag., pp. 46-56, Feb. 1990.

Index Terms:
multiple input signature analysis; probability; multiple-input compactors; error assumptions; VLSI circuits; binary memory elements; irreducible polynomial; error model; aliasing; standard linear algebra notions; built-in self test; feedback; logic testing; shift registers.
Citation:
T. Kameda, S. Pilarski, A. Ivanov, "Notes on Multiple Input Signature Analysis," IEEE Transactions on Computers, vol. 42, no. 2, pp. 228-234, Feb. 1993, doi:10.1109/12.204795
Usage of this product signifies your acceptance of the Terms of Use.