This Article 
 Bibliographic References 
 Add to: 
High-Speed Addition in CMOS
December 1992 (vol. 41 no. 12)
pp. 1612-1615

A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware.

[1] H. Ling, "High speed binary adder,"IBM J. Res. Develop., vol. 25, no. 3, pp. 156-166, May 1981.
[2] R. W. Doran, "Variants of an improved carry-look-ahead-sum adder,"IEEE Trans. Comput., vol. 37, no. 9, pp. 1110-1113, Sept. 1988.
[3] G. Bewick, P. Song, G. De Micheli, and M. J. Flynn, "Approaching a nanosecond: A 32 bit adder," inProc. ICCD Conf., 1988, pp. 221-224.
[4] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215-222.
[5] J. P. Uyemura,Fundamentals of MOS Digital Integrated Circuit. Reading, MA: Addison-Wesley, 1988, ch. 6-9.
[6] E. J. McCluskey,Logic Design Principles: with Emphasis on Testable Semi-Custom Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1986, pp. 448-450.
[7] I. S. Hwang and A. L. Fisher, "A 3.2 ns 32-bit CMOS adder in multiple output domino logic," in1988 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 140, 141, 332, and 333.
[8] V. G. Oklobdzija and E. R. Barnes. "Some optimal schemes for alu implementation in vlsi technology," inProc. of the 7th Symp. Comput. Arithmetic, June 1985, pp. 2-8.

Index Terms:
high speed addition; CMOS; static complementary metal-oxide semiconductor; Ling-type 32-bit adder; gate delay; serial transistors; worst-case critical path; carry look-ahead; 32 bit; adders; CMOS integrated circuits.
N.T. Quach, M.J. Flynn, "High-Speed Addition in CMOS," IEEE Transactions on Computers, vol. 41, no. 12, pp. 1612-1615, Dec. 1992, doi:10.1109/12.214671
Usage of this product signifies your acceptance of the Terms of Use.