Issue No.12 - December (1992 vol.41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.214671
<p>A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware.</p>
high speed addition; CMOS; static complementary metal-oxide semiconductor; Ling-type 32-bit adder; gate delay; serial transistors; worst-case critical path; carry look-ahead; 32 bit; adders; CMOS integrated circuits.
N.T. Quach, M.J. Flynn, "High-Speed Addition in CMOS", IEEE Transactions on Computers, vol.41, no. 12, pp. 1612-1615, December 1992, doi:10.1109/12.214671