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M.T. O'Keefe, J.A.B. Fortes, B.W. Wah, "On the Relationship Between Two Systolic Array Design Methodologies," IEEE Transactions on Computers, vol. 41, no. 12, pp. 15891593, December, 1992.  
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@article{ 10.1109/12.214667, author = {M.T. O'Keefe and J.A.B. Fortes and B.W. Wah}, title = {On the Relationship Between Two Systolic Array Design Methodologies}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {12}, issn = {00189340}, year = {1992}, pages = {15891593}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.214667}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On the Relationship Between Two Systolic Array Design Methodologies IS  12 SN  00189340 SP1589 EP1593 EPD  15891593 A1  M.T. O'Keefe, A1  J.A.B. Fortes, A1  B.W. Wah, PY  1992 KW  systolic array design methodologies; parameter method; data dependency method; optimization; optimal array; deconvolution algorithm; logic CAD; optimisation; parallel algorithms; systolic arrays. VL  41 JA  IEEE Transactions on Computers ER   
The parameter method and data dependency method have been proposed as systematic design methodologies for systolic arrays. The authors describe the relationship between the two methodologies and show that the parameter method applies to a subclass of the algorithms that can be processed by the dependency method. The optimization procedure of the parameter method can be applied, in a restricted sense, within the framework of the dependency method. This procedure is used to derive an optimal array for the deconvolution algorithm.
[1] G. J. Li and B. W. Wah, "The design of optimal systolic arrays,"IEEE Trans. Comput., vol. C34, pp. 6677, Jan. 1985.
[2] D. I. Moldovan and J. A. B. Fortes, "Partitioning and mapping algorithms into fixed size systolic arrays,"IEEE Trans. Comput., vol. C35, pp. 112, Jan. 1986.
[3] J. A. B. Fortes, K. S. Fu, and B. W. Wah, "Systematic approaches to the design of algorithmically specified systolic arrays," inProc. IEEE Int. Conf. Acoust., Speech, Signal Processing, Mar. 1985, pp. 26 29.
[4] S. K. Rao, "Regular iterative algorithms and their implementations on processor arrays," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1985.
[5] M. C. Chen, "Synthesizing VLSI architectures: Dynamic programming solver," inProc. 1986 Int. Conf. Parallel Processing, Aug. 1986, pp. 776784.
[6] S.Y. Kung,VLSI Array Processors, Prentice Hall, Englewood Cliffs, N.J. 1988.
[7] J. V. McCanny and J. G. McWhirter, "The derivation and utilization of bit level systolic array architectures," inProc. 1986 Int. Workshop Systolic Arrays, Oxford, England, July 1986, pp. 4759.
[8] J. A. B. Fortes and D. I. Moldovan, "Data broadcasting in linearly scheduled array processors," inProc. 11th Annu. Int. Symp. Comput. Architecture, June 1984.
[9] M. T. O'Keefe and J. A. B. Fortes, "A comparative study of two systematic design methodologies for systolic arrays," Masters Thesis, School of Electrical Engineering, Purdue Univ., May 1986.
[10] M. T. O'Keefe and J. A. B. Fortes, "A comparative study of two systematic design methodologies for systolic arrays," inProc. 1986 Int. Conf. Parallel Processing, Aug. 1986, pp. 672675.
[11] C. Guerra and R. Melhem, "Synthesizing nonuniform systolic designs," inProc. 1986 Int. Conf. Parallel Processing, Aug. 1986, pp. 765772.
[12] J. Delosme and I. Ipsen, "Efficient systolic arrays for the solution of Toeplitz systems: An illustration of a methodology for the construction of systolic architectures in VLSI," inProc. 1986 Int. Workshop Systolic Arrays, Oxford, England, July 1986, pp. 3746.
[13] P. R. Cappello and K. Steiglitz, "Unifying VLSI array designs with geometric transformations," inProc. 1983 Int. Conf. Parallel Processing, Aug. 1983, pp. 448457.
[14] Proc. Int. Conf. Application Specific Array Processors, M. Valero, Y. Kung, T. Lang, and J. A. B. Fortes, Eds., Sept. 1991, IEEE Catalog Number 9171633.