Issue No.12 - December (1992 vol.41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.214666
<p>An algorithm for bounding the random pattern testability of individual faults in a circuit is proposed. Auxiliary gates for bounding the testability are constructed, converting the problem into one of determining the signal probability at the output of the auxiliary gate. The results presented are in terms of lower bounds of the testabilities of faults. The bounds generated by the algorithm can be used by designers to identify pseudorandom pattern resistant faults, to enable them to modify the circuit structure to make the faults easy to detect, and, hence, to increase the fault coverage.</p>
bounding algorithm; circuit faults; signal probabilities; testability measurement; conditional syndromes; random pattern testability; auxiliary gate; lower bounds; pseudorandom pattern resistant faults; circuit structure; built-in self test; circuit analysis computing; computational complexity; integrated circuit testing.
R. Kapur, M.R. Mercer, "Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes", IEEE Transactions on Computers, vol.41, no. 12, pp. 1580-1588, December 1992, doi:10.1109/12.214666