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| A. Hlawiczka, "Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks," IEEE Transactions on Computers, vol. 41, no. 12, pp. 1562-1571, December, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/12.214664, author = {A. Hlawiczka}, title = {Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {12}, issn = {0018-9340}, year = {1992}, pages = {1562-1571}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.214664}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks IS - 12 SN - 0018-9340 SP1562 EP1571 EPD - 1562-1571 A1 - A. Hlawiczka, PY - 1992 KW - parallel signature analyzers; linear feedbacks; bottom-top exclusive OR; multiple input linear feedback shift register; top-bottom exclusive OR; XOR gates; reducible characteristic polynomial; error sequence aliasing; logic analysers; shift registers; signal processing equipment. VL - 41 JA - IEEE Transactions on Computers ER - | |||
A bottom-top exclusive OR (BTE) type multiple input linear feedback shift register (MISR) and a top-bottom exclusive OR (TBE) type MISR which use only (t+1)/2 XOR gates in their linear feedback are presented. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a BTE MISR are included. Infirmities of certain BTE type MISRs and TBE type MISRs with a reducible characteristic polynomial have been made. The proof that the probability of error sequence aliasing on a single input of BTE or TBE type MISR, where a characteristic polynomial of degree n is reducible, asymptotically approaches a value greater or equal to 2/sup -n/ is also given.
[1] L.-T. Wang and E. J. McCluskey, "Hybrid designs generating maximum-length sequences,"IEEE Trans. Comput.-Aided Design, vol. 7, pp. 91-99, Jan. 1988.
[2] T. Sridhar and D. S. Ho, "Analysis and simulation of parallel signature analyzers" inProc. 1982 IEEE Test Conf., p. 656.
[3] S. Z. Hassan, D. J. Lu, and E. J. McCluskey, "Parallel signature analyzers detection capability and extensions," inProc. COMPCON, 1983, Spring, p. 440.
[4] A. Hlawiczka, "Compression of three-state data serial streams by mean of a parallel LFSR signature analyzer,"IEEE Trans. Comput., vol. C-35, no. 8, p. 732, Aug. 1986.
[5] T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, "Aliasing errors in signature analysis registers,"IEEE Comput. Design and Test, p. 39, Apr. 1987.
[6] A. Hlawiczka, "Hybrid design of parallel signature analyzers," inProc. IEEE Euro. Test Conf., Apr 1989, pp. 346-360.
[7] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.

