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Learning Probabilistic RAM Nets Using VLSI Structures
December 1992 (vol. 41 no. 12)
pp. 1552-1561

Hardware-realizable learning probabilistic RAMs (pRAMs) which implement local reinforcement rules utilizing synaptic rather than threshold noise in the stochastic search procedure are described. The design allows for both global and local rewards and penalties (in this latter case implementing a modified version of backpropagation). The architecture allows for serial updating of the weights of a pRAM net according to a reward/penalty learning rule. It is possible to generate a new set of pRAM outputs at least every 100 mu s, which is faster than the response time of biological neurons.

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Index Terms:
synaptic noise; global rewards; global penalties; local penalties; RAM nets; VLSI structures; learning probabilistic RAMs; local reinforcement rules; stochastic search; local rewards; backpropagation; serial updating; weights; learning rule; backpropagation; content-addressable storage; neural nets; VLSI.
Citation:
T.G. Clarkson, D. Gorse, J.G. Taylor, C.K. Ng, "Learning Probabilistic RAM Nets Using VLSI Structures," IEEE Transactions on Computers, vol. 41, no. 12, pp. 1552-1561, Dec. 1992, doi:10.1109/12.214663
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