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Efficient Instruction Sequencing with Inline Target Insertion
December 1992 (vol. 41 no. 12)
pp. 1537-1551

Inline target insertion, a specific compiler and pipeline implementation method for delayed branches with squashing, is defined. The method is shown to offer two important features not discovered in previous studies. First, branches inserted into branch slots are correctly executed. Second, the execution returns correctly from interrupts or exceptions with only one program counter. These two features result in better performance and less software/hardware complexity than conventional delayed branching mechanisms.

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Index Terms:
instruction sequencing; inline target insertion; compiler; pipeline; delayed branches; squashing; branch slots; interrupts; exceptions; program counter; parallel programming; pipeline processing; program compilers.
Citation:
W.W. Hwu, P.P. Chang, "Efficient Instruction Sequencing with Inline Target Insertion," IEEE Transactions on Computers, vol. 41, no. 12, pp. 1537-1551, Dec. 1992, doi:10.1109/12.214662
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