This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
December 1992 (vol. 41 no. 12)
pp. 1527-1536

An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

[1] Z. Barzilai and B. K. Rosen, "Comparison of AC self-testing procedures," inProc. IEEE Int. Test Conf., Oct. 1983, pp. 89-91.
[2] J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar, "Transition fault simulation,"IEEE Design and Test, pp. 32-38, Apr. 1987.
[3] M. Schulz and F. Brglez, "Accelerated Transition Fault Simulation,"Proc. Design Automation Conf., 1987, pp. 237-250.
[4] S. Koeppe, "Modeling and simulation of delay faults in CMOS logic circuits," inProc. IEEE Int. Test Conf., Sept. 1986, pp. 530-536.
[5] J. L. Carter, V. S. Iyengar, and B. K. Rosen, "Efficient test coverage determination for delay faults," inProc. IEEE Int. Test Conf., Sept. 1987, pp. 418-427.
[6] V. S. Iyengar, B. K. Rosen, and I. Spillinger, "Delay test generation 1--Concepts and coverage metrics," inProc. Int. Test Conf., 1988, pp. 857-866.
[7] V. S. Iyengar, B. K. Rosen, and I. Spillinger, "Delay test generation 2-Algebra and algorithms," inProc. IEEE Int. Test Conf., Sept. 1988, pp. 867-876.
[8] A.K. Pramanick and S.M. Reddy, "On the Detection of Delay Faults,"Proc. Int'l Test Conf., IEEE CS Press, 1988, pp. 845- 856.
[9] F. Fink, K. Fuchs, and M. H. Schulz, "An efficient parallel pattern gate delay fault simulator with accelerated detected fault size determination capabilities," inProc. 2nd Europ. Test Conf., Apr. 1991.
[10] J. J. Shedletsky and J. D. Lesser, "An experimental delay test generator for LSI logic,"IEEE Trans. Comput., vol. C-29, no. 3, pp. 235-248, Mar. 1980.
[11] C. J. Lin and S. M. Reddy, "On delay testing in logic circuits,"IEEE Trans. Comput.-Aided Design, vol. CAD-6, no. 5, pp. 694-703, 1987.
[12] S. M. Reddy, C. J. Lin, and S. Patil, "An automatic test pattern generator for the detection of path delay faults," inProc. IEEE Int. Conf. CAD, Nov. 1987, pp. 284-287.
[13] E. S. Park and M. R. Mercer, "Robust and nonrobust tests for path delay faults in a combinational circuit," inProc. IEEE Int. Test Conf., Sept. 1987, pp. 1027-1034.
[14] M. H. Schulz, K. Fuchs, and F. Fink, "Advanced automatic test pattern generation techniques for path delay faults," inProc. 19th FTCS, June 1989.
[15] K. Fuchs, F. Fink, and M.H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults,"IEEE Trans. CAD, Vol. CAD-10, No. 10, Oct. 1991, pp. 1323- 1335.
[16] G. L. Smith, "Model for delay faults based upon paths," inProc. IEEE Int. Test Conf., Sept. 1985, pp. 342-349.
[17] M. H. Schulz, F. Fink, and K. Fuchs, "Parallel pattern fault simulation of path delay faults," inProc. 26th DAC, June 1989.
[18] J. Savir and W. H. McAnney, "Random pattern testability of delay faults,"IEEE Trans. Comput., vol. 37, no. 3, pp. 291-300, Mar. 1988.
[19] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," inProc. IEEE Symp. Circuits and Systems; Special Session on ATPG and Fault Simulation, June 1985, pp. 663-698.

Index Terms:
path delay fault simulation; parallel processing; patterns; circuit analysis computing; fault location; integrated circuit testing; many-valued logics; parallel processing.
Citation:
F. Fink, K. Fuchs, M.H. Schulz, "Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns," IEEE Transactions on Computers, vol. 41, no. 12, pp. 1527-1536, Dec. 1992, doi:10.1109/12.214661
Usage of this product signifies your acceptance of the Terms of Use.