This Article 
 Bibliographic References 
 Add to: 
Processor Architecture and Data Buffering
October 1992 (vol. 41 no. 10)
pp. 1211-1222

The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefore are not applicable for low-density technologies. It is also shown that software support can bridge the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local storage allocated interprocedurally outperforms scalable architectures with equal sized local memories and even some with larger sized local memories. When a small cache is added to an unscalable architecture, their performance advantage becomes significant.

[1] D. R. Ditzel and H. R. McLellan, "Register allocation for free: The C Machine stack cache," inProc., Symp. Architectural Support for Programming Languages and Oper. Syst., Mar. 1982, pp. 48-56.
[2] A. D. Berenbaum, D. R. Ditzel, and H. R. Mclellan," "Introduction to the CRISP instruction set architecture," inProc. COMPCON 1987, Jan. 1987, pp. 86-90.
[3] D. Alpert, "Memory hierarchies for directly executed language microprocessors," Tech. Rep. 84-260, Comput. Syst. Lab., Stanford Univ., Stanford, CA 94305, June 1984.
[4] D. A. Patterson and C. H. Sequin, "RISC I: A reduced instruction set VLSI computer," inProc. 8th Annu. Int. Symp. Comput. Architecture, May 1981, pp. 443-457.
[5] J. M. Mulder, "Tradeoffs in processor-architecture and data-buffer design," Tech. Rep. 87-345, Comput. Syst. Lab., Stanford Univ., Stanford, CA 94305, Dec. 1987.
[6] C. L. Mitchell and M. J. Flynn, "A workbench for computer architects,"IEEE Design&Test, vol. 5, no. 1, pp. 19-29, Feb. 1988.
[7] B. Bray, K. Cuderman, M. Flynn, and A. Zimmerman, "The computer Architect's Workbench," inInformation Processing 89 (IPIP), G. X. Ritter, Ed. Amsterdam, The Netherlands: Elsevier Science Publishers B. V., (North-Holland), Sept. 1989.
[8] F. C. Chow, "A portable machine-independent global optimizer-Design and measurements," Tech. Rep. 83-254, Comput. Syst. Lab., Stanford Univ., Stanford, CA 94305, Dec. 1983.
[9] G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, E. Hopkins, and P. W. Markstein, "Register allocation via coloring,"Comput. Languages, vol. 6, pp. 47-51, 1981.
[10] F. Chow and J. Hennessy, "Register allocation by priority-based coloring,"SIGPLAN Not., vol. 19, no. 6, pp. 222-232, 1984.
[11] D. Wall, "Global register allocation at link time," inProc. SIGPLAN'86 Symp. Compiler Construction, ACM, June 1986, pp. 264-275.
[12] P. Steenkiste and J. Hennessy, "A simple interprocedural register allocation algorithm and its effectiveness for lisp,"Trans. Programming Languages and Syst., vol. 11, no. 1, pp. 1-32, Jan. 1989.
[13] F. C. Chow, "Minimizing register-usage penalty at procedure calls," inProc. SYSPLAN '88: Conf. Programming Language Design and Implementation, June 1988, pp. 85-94.
[14] M.G.H. Katevenis,Reduced Instruction Set Computer Architectures for VLSI, doctoral dissertation, Univ. of California, Berkeley, Calif., 1983.
[15] D. C. Halbert and P. B. Kessler, "Windows of overlapping register frames," Tech. rep., Comput. Sci. Division, Univ. of California Berkeley, CA 94720, 1980.
[16] J. M. Mulder, "Data buffering: Software versus hardware support," inProc., Conf. Architecture Support for Programming Languages and Oper. Syst., Apr. 1989, pp. 144-151.
[17] M. J. Flynn, C. L. Mitchel, and J. M. Mulder, "And now a case for more complex instructions,"IEEE Comput. Mag., vol. 20, no. 9, pp. 71-83, Sept. 1987.
[18] J. M. Mulder, N. T. Quach, and M. J. Flynn, "An area model for on-chip memories,"J. Solid State Circuits, vol. 26, no. 2, pp. 98-106, Feb. 1991.
[19] M. D. Hill and A. J. Smith, "Experimental evaluation of on-chip microprocessor cache memories," inProc. 11th Annu. Int. Symp. Comput. Architecture, June 1984, pp. 158-166.
[20] M. J. Flynn and D. Alpert, "Performance trade-offs for microprocessor cache memories,"IEEE Micro, vol. 8, no. 4, pp. 44-54, Aug. 1988.
[21] C. Mitchell and M. Flynn, "The effects of processor architecture on memory traffic,"Trans. Comput. Syst., vol. 8, no. 3, pp. 230-250, Aug. 1990.

Index Terms:
data buffering; memory hierarchy; performance; scalability; stack; register; memory-to-memory; software support; buffer storage; computer architecture; data structures.
H. Mulder, M.J. Flynn, "Processor Architecture and Data Buffering," IEEE Transactions on Computers, vol. 41, no. 10, pp. 1211-1222, Oct. 1992, doi:10.1109/12.166600
Usage of this product signifies your acceptance of the Terms of Use.