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Processor Architecture and Data Buffering
October 1992 (vol. 41 no. 10)
pp. 1211-1222

The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require at least 32 words of local memory and therefore are not applicable for low-density technologies. It is also shown that software support can bridge the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local storage allocated interprocedurally outperforms scalable architectures with equal sized local memories and even some with larger sized local memories. When a small cache is added to an unscalable architecture, their performance advantage becomes significant.

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Index Terms:
data buffering; memory hierarchy; performance; scalability; stack; register; memory-to-memory; software support; buffer storage; computer architecture; data structures.
Citation:
H. Mulder, M.J. Flynn, "Processor Architecture and Data Buffering," IEEE Transactions on Computers, vol. 41, no. 10, pp. 1211-1222, Oct. 1992, doi:10.1109/12.166600
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