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Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor
October 1992 (vol. 41 no. 10)
pp. 1201-1210

A simple but powerful architecture based on the classical associative processor model is proposed. By distributing logic among slices of storage cells such that a number of bit-planes share a simple logic unit, bit-parallel arithmetic for massively parallel processing becomes feasible. For m-bit operands, this architecture enables complex operations such as multiplication and division to execute in O(m) cycles as opposed to O(m/sup 2/) for bit-serial machines. Algorithms which utilize this bit-parallel property to efficiently perform operations on floating point data have been developed. The simplicity of the architecture enables its implementation using VLSI technology, and hence allows the construction of a word-parallel, bit-parallel, massively parallel (P/sup 3/) computing system. Implementations of the fast Fourier transform and matrix multiplication are presented to illustrate the operation of this system.

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Index Terms:
bit-parallel arithmetic; massively-parallel associative processor; storage cells; multiplication; division; floating point data; VLSI; fast Fourier transform; matrix multiplication; digital arithmetic; fast Fourier transforms; parallel architectures; VLSI.
I.D. Scherson, D.A. Kramer, B.D. Alleyne, "Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor," IEEE Transactions on Computers, vol. 41, no. 10, pp. 1201-1210, Oct. 1992, doi:10.1109/12.166599
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