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I.D. Scherson, D.A. Kramer, B.D. Alleyne, "BitParallel Arithmetic in a MassivelyParallel Associative Processor," IEEE Transactions on Computers, vol. 41, no. 10, pp. 12011210, October, 1992.  
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@article{ 10.1109/12.166599, author = {I.D. Scherson and D.A. Kramer and B.D. Alleyne}, title = {BitParallel Arithmetic in a MassivelyParallel Associative Processor}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {10}, issn = {00189340}, year = {1992}, pages = {12011210}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.166599}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  BitParallel Arithmetic in a MassivelyParallel Associative Processor IS  10 SN  00189340 SP1201 EP1210 EPD  12011210 A1  I.D. Scherson, A1  D.A. Kramer, A1  B.D. Alleyne, PY  1992 KW  bitparallel arithmetic; massivelyparallel associative processor; storage cells; multiplication; division; floating point data; VLSI; fast Fourier transform; matrix multiplication; digital arithmetic; fast Fourier transforms; parallel architectures; VLSI. VL  41 JA  IEEE Transactions on Computers ER   
A simple but powerful architecture based on the classical associative processor model is proposed. By distributing logic among slices of storage cells such that a number of bitplanes share a simple logic unit, bitparallel arithmetic for massively parallel processing becomes feasible. For mbit operands, this architecture enables complex operations such as multiplication and division to execute in O(m) cycles as opposed to O(m/sup 2/) for bitserial machines. Algorithms which utilize this bitparallel property to efficiently perform operations on floating point data have been developed. The simplicity of the architecture enables its implementation using VLSI technology, and hence allows the construction of a wordparallel, bitparallel, massively parallel (P/sup 3/) computing system. Implementations of the fast Fourier transform and matrix multiplication are presented to illustrate the operation of this system.
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