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Synergistic Fault-Tolerance for Memory Chips
September 1992 (vol. 41 no. 9)
pp. 1078-1087

The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism.

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Index Terms:
bitline redundancy; memory chips; synergistic fault tolerance; VLSI memory chip; error-correction; error-correcting codes; redundant circuits; wordline redundancy; fault-tolerance synergism; DRAM chips; error correction codes; fault tolerant computing; VLSI.
Citation:
C.H. Stapper, H.-S. Lee, "Synergistic Fault-Tolerance for Memory Chips," IEEE Transactions on Computers, vol. 41, no. 9, pp. 1078-1087, Sept. 1992, doi:10.1109/12.165390
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