This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic
August 1992 (vol. 41 no. 8)
pp. 1040-1050

Various features found in standard floating point arithmetic (IEEE 754) are examined in light of their appropriateness for sign/logarithm arithmetic. The emphasis is on a 32-b word size comparable to IEEE 754 single precision, although other word sizes are possible. A multilayer sign/logarithm format is considered. The lowest layer, similar to previous implementations, would provide only normalized representations but would not provide representations for zero, denormalized values, infinities, and NaNs. The highest layer would provide most of the features found in IEEE 754, including zeros, denormalized values, infinities, and NaNs. Novel algorithms for implementing logarithmic denormalized arithmetic are presented. Simulation results show that the error characteristics of the proposed logarithmic denormalized arithmetic algorithms are similar to those of the denormalized floating point arithmetic in IEEE 754.

[1] M. G. Arnold. "Extending the precision of the sign logarithm number system," M.S. thesis, Univ. Wyoming, Laramie, 1982.
[2] M. G. Arnold, T. A. Bailey, J. R. Cowles, and J. J. Cupal. "Redundant logarithmic arithmetic,"IEEE Trans. Comput., vol. 39. pp. 1077-1086, Aug. 1990.
[3] M. Arnold, T. Bailey, J. Cowles, and J. Cupal, "Implementing back propagation neural nets with logarithmic arithmetic," inProc. Int. AMSE Conf. Neural Networks, San Diego, CA, May 29-31, 1991.
[4] J. L. Barlow and E. H. Bareiss, "On roundoff distribution in floating point and logarithmic arithmetic,"Computing, vol. 34, pp. 325-364, 1985.
[5] J. T. Coonen, "Underflow and the denormalized numbers,"IEEE Comput. Mag., vol 14, no. 3, pp. 75-87, Mar. 1981.
[6] A. D. Edgar and S. C. Lee, "FOCUS microcomputer number system,"Commun. ACM, vol. 22, pp. 166-177, Mar. 1979.
[7] "Fast floating point C functions."BYTE, vol. 16, no. 7, p. 72MW-8, July 1991.
[8] "FFP 1.0," Triakis, Bothell, WA, 1991.
[9] "FastMath Software Benchmark Report,"FastMath, Fort Collins, CO, 1991.
[10] D. Feucht, "Logarithmic number representations in Forth,"J. Forth Appl. Res., vol. 5, no. 2, pp. 271-286, 1988.
[11] IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985, IEEE, 1985.
[12] S. J. Kidd, "Implementation of the sign-logarithm arithmetic FFT,"Royal Signals and Radar Establishment Memorandum 3644, Malvern: 1983.
[13] N. G. Kingsbury and P. J. W. Rayner, "Digital filtering using logarith, metic arithmetic,"Electron. Lett., vol. 7. pp. 56-58, Jan. 1971.
[14] T. Kurokawa and T. Mizukoshi "A fast and simple method for curve drawing-A new approach using logarithmic number systems,"J. Inform. Processing, vol. 14, pp. 144-152, 1991.
[15] T. Kurokawa, J. A. Payne, and S. C. Lee, "Error analysis of recursive digital filters implemented with logarithmic number systems,"IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-28, pp. 706-715, Dec. 1980.
[16] Language Compatible Arithmetic Standard. version 3.0, X3T2/91-006, ISO/IECJTC1/SC22/WG11/N212, American National Standards Institute, Dec. 26, 1990.
[17] S. C. Lee and A. D. Edgar, "The FOCUS number system,"IEEE Trans. Comput., vol. C-26, pp. 1167-1170, Nov. 1977.
[18] Z. Leonelli, Supplémente Logarithmique, a reprint of Leonelli's 1803 manuscript with a biography by J. Hoüel, Gauthier-Villars. Paris, 1875.
[19] D. M. Lewis, "Hardware accelerators for timing simulation of VLSI digital circuits,"IEEE Trans. Comput.-Aided Design, vol. 7, no. 11, pp. 1134-1149, Nov. 1988.
[20] D. Lewis and L. Yu, "Algorithm design for a 30-bit integrated logarithmic processor," inProc. 9th Symp. Comput. Arithmetic, 1989, pp. 192-199.
[21] D. M. Lewis. "An architecture for addition and subtraction of long word length numbers in the logarithmic number system,"IEEE Trans. Comput., pp. 1325-1336, 1990.
[22] J. D. Marasa and D. W. Matula, "A simulative study of correlated error in various finite-precision arithmetics,"IEEE Trans. Comput., vol. C-22, pp. 587-597, June 1973.
[23] R. E. Morley, Jr., G. L. Engel, T. J. Sullivan, and S. M. Natarajan, "VLSI based design of a battery-operated digital hearing aid," inProc. ICASSP, New York, 1988, pp. 2512-2515.
[24] H. Murveitet al., "A large-vocabulary real-time continuous-speech recognition system," inProc. ICASSP, Glasgow, 1989, pp. 789-792.
[25] G. M. Papadourakis and H. Andre, "High speed implementation of matrix inversion algorithms in orthogonal systolic architectures," inProc. IEEE Southeastern Conf., IEEE catalog 88CH2571-8, 1988, pp 200-204.
[26] L. Pickett, "Soft co-processors," Log Point Systems, Mountain View, CA. 1989.
[27] T. Stouraitis, "Logarithmic number system theory, analysis, and design," Ph.D. dissertation, Univ. Florida, Gainesville, 1986.
[28] E. Swartzlander and A. G. Alexopoulos, "The sign/logarithm number system,"IEEE Trans. Comput., vol. C-24, pp. 1238-1242, Dec. 1975.
[29] E. E. Swartzlanderet al., "Arithmetic for ultrahigh speed tomography,"IEEE Trans. Comput., vol. C-29, pp. 341-353, May 1980.
[30] E. E. Swartzlander, D. Chandra, T. Nagle, and S. A. Starks, "Sign/logarithm arithmetic for FFT implementation,"IEEE Trans. Comput., vol. C-32, pp. 526-534, 1983.
[31] F. J. Taylor. R. Gill, J. Joseph, and J. Radke, "A 20 bit logarithmic number system processor,"IEEE Trans. Comput., vol. C-37, pp. 190-199, 1988.

Index Terms:
IEEE 754; sign/logarithm arithmetic; standard floating point arithmetic; multilayer sign/logarithm format; zeros; denormalized values; infinities; NaNs; logarithmic denormalized arithmetic algorithms; 32 bit; digital arithmetic; number theory; standards.
Citation:
M.G. Arnold, T.A. Bailey, J.R. Cowles, M.D. Winkel, "Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic," IEEE Transactions on Computers, vol. 41, no. 8, pp. 1040-1050, Aug. 1992, doi:10.1109/12.156547
Usage of this product signifies your acceptance of the Terms of Use.