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Issue No.08 - August (1992 vol.41)
pp: 1040-1050
ABSTRACT
<p> Various features found in standard floating point arithmetic (IEEE 754) are examined in light of their appropriateness for sign/logarithm arithmetic. The emphasis is on a 32-b word size comparable to IEEE 754 single precision, although other word sizes are possible. A multilayer sign/logarithm format is considered. The lowest layer, similar to previous implementations, would provide only normalized representations but would not provide representations for zero, denormalized values, infinities, and NaNs. The highest layer would provide most of the features found in IEEE 754, including zeros, denormalized values, infinities, and NaNs. Novel algorithms for implementing logarithmic denormalized arithmetic are presented. Simulation results show that the error characteristics of the proposed logarithmic denormalized arithmetic algorithms are similar to those of the denormalized floating point arithmetic in IEEE 754.</p>
INDEX TERMS
IEEE 754; sign/logarithm arithmetic; standard floating point arithmetic; multilayer sign/logarithm format; zeros; denormalized values; infinities; NaNs; logarithmic denormalized arithmetic algorithms; 32 bit; digital arithmetic; number theory; standards.
CITATION
T.A. Bailey, J.R. Cowles, M.G. Arnold, "Applying Aeatures of IEEE 754 to Sign/Logarithm Arithmetic", IEEE Transactions on Computers, vol.41, no. 8, pp. 1040-1050, August 1992, doi:10.1109/12.156547
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