Issue No.08 - August (1992 vol.41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.156543
<p>Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described.</p>
parallel architecture; CORDIC algorithms; constant scale factor; redundant addition; latency time; adders; computational complexity; digital arithmetic; iterative methods; number theory.
H. Hahn, B.J. Hosticka, "Low Latency Time CORDIC Algorithms", IEEE Transactions on Computers, vol.41, no. 8, pp. 1010-1015, August 1992, doi:10.1109/12.156543