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D. Timmermann, H. Hahn, B.J. Hosticka, "Low Latency Time CORDIC Algorithms," IEEE Transactions on Computers, vol. 41, no. 8, pp. 10101015, August, 1992.  
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@article{ 10.1109/12.156543, author = {D. Timmermann and H. Hahn and B.J. Hosticka}, title = {Low Latency Time CORDIC Algorithms}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {8}, issn = {00189340}, year = {1992}, pages = {10101015}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.156543}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Low Latency Time CORDIC Algorithms IS  8 SN  00189340 SP1010 EP1015 EPD  10101015 A1  D. Timmermann, A1  H. Hahn, A1  B.J. Hosticka, PY  1992 KW  parallel architecture; CORDIC algorithms; constant scale factor; redundant addition; latency time; adders; computational complexity; digital arithmetic; iterative methods; number theory. VL  41 JA  IEEE Transactions on Computers ER   
Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described.
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