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M.A. Hasan, V.K. Bhargava, "BitSerial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)," IEEE Transactions on Computers, vol. 41, no. 8, pp. 972980, August, 1992.  
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@article{ 10.1109/12.156540, author = {M.A. Hasan and V.K. Bhargava}, title = {BitSerial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {8}, issn = {00189340}, year = {1992}, pages = {972980}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.156540}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  BitSerial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/) IS  8 SN  00189340 SP972 EP980 EPD  972980 A1  M.A. Hasan, A1  V.K. Bhargava, PY  1992 KW  circuit complexity; time complexity; chip fabrication; finite fields; systolic structure; bitserial division; control signal; bitserial systolic multiplier; computational complexity; digital arithmetic; dividing circuits; multiplying circuits. VL  41 JA  IEEE Transactions on Computers ER   
A systolic structure for bitserial division over the field GF(2/sup m/) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m/sup 2/ and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bitserial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area.
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