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Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)
August 1992 (vol. 41 no. 8)
pp. 972-980

A systolic structure for bit-serial division over the field GF(2/sup m/) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m/sup 2/ and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bit-serial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area.

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Index Terms:
circuit complexity; time complexity; chip fabrication; finite fields; systolic structure; bit-serial division; control signal; bit-serial systolic multiplier; computational complexity; digital arithmetic; dividing circuits; multiplying circuits.
M.A. Hasan, V.K. Bhargava, "Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)," IEEE Transactions on Computers, vol. 41, no. 8, pp. 972-980, Aug. 1992, doi:10.1109/12.156540
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