
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Z.J. Mou, F. Jutand, "'OverturnedStairs' Adder Trees and Multiplier Design," IEEE Transactions on Computers, vol. 41, no. 8, pp. 940948, August, 1992.  
BibTex  x  
@article{ 10.1109/12.156536, author = {Z.J. Mou and F. Jutand}, title = {'OverturnedStairs' Adder Trees and Multiplier Design}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {8}, issn = {00189340}, year = {1992}, pages = {940948}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.156536}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  'OverturnedStairs' Adder Trees and Multiplier Design IS  8 SN  00189340 SP940 EP948 EPD  940948 A1  Z.J. Mou, A1  F. Jutand, PY  1992 KW  VLSI circuit layout; Wallace trees; multioperand adders; OverturnedStairs trees; 2's complement parallel multiplier; adders; digital arithmetic; logic design; multiplying circuits; trees (mathematics); VLSI. VL  41 JA  IEEE Transactions on Computers ER   
Wallace trees are the theoretically fastest multioperand adders. However, their complex interconnections do not permit practical implementations. A family of OverturnedStairs trees which achieve the same speed performance as equivalent Wallace trees in many cases, but require a simple and regular interconnection scheme is introduced. These trees can be designed in a systematic way and laid out regularly in a VLSI circuit. A comparison is made between various trees to provide useful indexes for a practical design. The design of a 16*16 2's complement parallel multiplier using OverturnedStairs trees is studied as an illustration.
[1] C.S. Wallace, "A suggestion for a fast multiplier,"IEEE Trans. Electron. Comput., pp. 1417, Feb. 1964.
[2] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215222.
[3] P. Reusens, W. H. Ku, and Y. H. Mao, "Fixedpoint highspeed parallel multipliers in VLSI," inVLSI Systems and Computations, H. T. Kunget al., Eds. New York: SpringerVerlag, 1981, pp. 301310.
[4] D. Zuras and W. H. McAllister, "Balanced delay trees and combinatorial division in VLSI,"IEEE J. SolidState Circuits, pp. 814819, Oct. 1986.
[5] W. Li, J.B. Burr, and A. Peterson, "A fully parallel VLSI implementation of distributed arithmetic," inProc. IEEE Int. Conf. Circuits Syst., Espoo, Finland, 1988, pp. 15111515.
[6] M. Santoro and M. Horowitz, "SPIM: A pipelined 64×64bit iterative multiplier,"IEEE J. SolidState Circuits, pp. 487493, Apr. 1989.
[7] L. Dadda, "Some schemes for parallel multipliers,"Alta Frequenza, vol. 19, pp. 349356, Mar. 1965.
[8] L. Dadda, "Fast multipliers to two's complement numbers in serial form," inProc. IEEE 7th Symp. Comput. Arithmetic, June 1985, pp. 5763.
[9] W.J. Stenzelet al., "A compact highspeed multiplication scheme,"IEEE Trans. Comput., vol. C26, pp. 948957, Oct. 1977.
[10] Y. Harataet al., "A highspeed multiplier using a redundant binary adder tree,"IEEE J. SolidState Circuits, vol. SC22, pp. 2834, Feb. 1987.
[11] J. Vuillemin, "A very fast multiplication algorithm for VLSI implementation,"Integration, vol. 1, pp. 3952, 1983.
[12] C. H. Baugh and B. Wooley, "A two's complement parallel array multiplication algorithm,"IEEE Trans. Comput., vol. C22, pp. 10451047, 1973.