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Issue No.08 - August (1992 vol.41)
pp: 940-948
ABSTRACT
<p>Wallace trees are the theoretically fastest multioperand adders. However, their complex interconnections do not permit practical implementations. A family of Overturned-Stairs trees which achieve the same speed performance as equivalent Wallace trees in many cases, but require a simple and regular interconnection scheme is introduced. These trees can be designed in a systematic way and laid out regularly in a VLSI circuit. A comparison is made between various trees to provide useful indexes for a practical design. The design of a 16*16 2's complement parallel multiplier using Overturned-Stairs trees is studied as an illustration.</p>
INDEX TERMS
VLSI circuit layout; Wallace trees; multioperand adders; Overturned-Stairs trees; 2's complement parallel multiplier; adders; digital arithmetic; logic design; multiplying circuits; trees (mathematics); VLSI.
CITATION
Z.-J. Mou, F. Jutand, "'Overturned-Stairs' Adder Trees and Multiplier Design", IEEE Transactions on Computers, vol.41, no. 8, pp. 940-948, August 1992, doi:10.1109/12.156536
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