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P.K. Chan, M.D.F. Schlag, C.D. Thomborson, V.G. Oklobdzija, "Delay Optimization of CarrySkip Adders and Block CarryLookahead Adders Using Multidimensional Dynamic Programming," IEEE Transactions on Computers, vol. 41, no. 8, pp. 920930, August, 1992.  
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@article{ 10.1109/12.156534, author = {P.K. Chan and M.D.F. Schlag and C.D. Thomborson and V.G. Oklobdzija}, title = {Delay Optimization of CarrySkip Adders and Block CarryLookahead Adders Using Multidimensional Dynamic Programming}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {8}, issn = {00189340}, year = {1992}, pages = {920930}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.156534}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Delay Optimization of CarrySkip Adders and Block CarryLookahead Adders Using Multidimensional Dynamic Programming IS  8 SN  00189340 SP920 EP930 EPD  920930 A1  P.K. Chan, A1  M.D.F. Schlag, A1  C.D. Thomborson, A1  V.G. Oklobdzija, PY  1992 KW  delay optimisation; carryskip adders; block carrylookahead adders; multidimensional dynamic programming; worstcase carry propagation delays; minimum latency; critical path delay; gate delays; fanin; fanout; adders; carry logic; digital arithmetic; dynamic programming. VL  41 JA  IEEE Transactions on Computers ER   
The worstcase carry propagation delays in carryskip adders and block carrylookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.
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