This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On the Testability of One-Dimensional ILAs for Multiple Sequential Faults
July 1992 (vol. 41 no. 7)
pp. 906-916

It is shown that one-dimensional, unilateral iterative logic arrays (ILAs) of combinational cells are C-testable for multiple sequential faults, provided the fault-free cell functions satisfy appropriate conditions. The test sequence is of length O((m/sup 2/n/sup 2/+mn/sup 3/)*K), where n (resp. m) is the number of signal values that can be applied to the horizontal (resp. vertical) cell input and K>or=n-1. Linear testability is also considered. The ripple-carry adder circuit (n=2, m=4) is shown to be C-testable with 699 test vectors.

[1] P. Banerjee and J. A. Abraham, "Characterization and testing of physical failures in MOS logic circuits,"IEEE Design Test, pp. 76-86, Aug. 1984.
[2] A. Chatterjee and J. A. Abraham, "NCUBE: An automatic test generation program for iterative logic arrays," inProc. International Conf. Compuer-Aided Design, Santa Clara, CA, Nov. 1988, pp. 428-431.
[3] W. T. Cheng and J. H. Patel, "Testing in two-dimensional iterative logic arrays," inProc. 1986 Int. Symp. Fault-Tolerant Comput. Syst., pp. 76-81.
[4] W. T. Cheng and J. H. Patel, "A shortest length test sequence for sequential-fault detection in ripple carry adders," inProc. 1985 Int. Conf. Comput. Aided Design, pp. 71-73.
[5] H. Elhuni, A. Vergis, and L. Kinney, "C-testability of two-dimensional iterative arrays,"IEEE Trans. Comput.-Aided Design, vol. CAD-5, no. 4, pp. 573-581, Oct. 1986.
[6] W.-K. Huang and F. Lombardi, "On an improved design approach for C-testable orthogonal iterative arrays,"IEEE Trans. Comput.-Aided Design, vol. CAD-7, no. 5, pp. 609-615, May 1988.
[7] W. H. Kautz, "Testing for faults in cellular logic arrays," inProc. 8th Annu. Symp. Switching and Automata Theory, 1967, pp. 161-174.
[8] A. Vergis and K. Steiglitz, "Testability conditions for bilateral arrays of combinational cells,"IEEE Trans. Comput., vol. C-35, no. 1, pp. 13-22, Jan. 1986.
[9] C-.W. Wu and P. R. Cappello, "Easily testable iterative logic arrays,"IEEE Trans. Comput., vol. C-39, pp. 640-652, May 1990.
[10] A. D. Friedman, "Easily testable iterative systems,"IEEE Trans. Comput., vol. C-22, pp. 1061-1064, Dec. 1973.
[11] A. Vergis, "On the testability of one-dimensional ILA's for multiple sequential faults," Tech. Rep. 89-9, Univ. Minnesota, Mar. 1989.

Index Terms:
linear testability; testability; one-dimensional ILAs; multiple sequential faults; combinational cells; C-testable; fault-free cell functions; ripple-carry adder circuit; adders; logic arrays; logic testing.
Citation:
A. Vergis, "On the Testability of One-Dimensional ILAs for Multiple Sequential Faults," IEEE Transactions on Computers, vol. 41, no. 7, pp. 906-916, July 1992, doi:10.1109/12.256448
Usage of this product signifies your acceptance of the Terms of Use.