|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| N. Kanopoulos, D. Pantzartzis, F.R. Bartram, "Design of Self-Checking Circuits Using DCVS Logic: A Case Study," IEEE Transactions on Computers, vol. 41, no. 7, pp. 891-896, July, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/12.256445, author = {N. Kanopoulos and D. Pantzartzis and F.R. Bartram}, title = {Design of Self-Checking Circuits Using DCVS Logic: A Case Study}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {7}, issn = {0018-9340}, year = {1992}, pages = {891-896}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.256445}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Design of Self-Checking Circuits Using DCVS Logic: A Case Study IS - 7 SN - 0018-9340 SP891 EP896 EPD - 891-896 A1 - N. Kanopoulos, A1 - D. Pantzartzis, A1 - F.R. Bartram, PY - 1992 KW - self-checking circuits; DCVS logic; differential cascode voltage switch; fault tolerance; low hardware-overhead costs; error correction; error detection; fault tolerant computing; logic circuits; logic design. VL - 41 JA - IEEE Transactions on Computers ER - | |||
A technique for designing self-checking circuits using differential cascode voltage switch (DCVS) logic is presented. This technique is used in a design case study and the results obtained through actual implementation and testing of a self-checking circuit are discussed. It is demonstrated that the self-checking capability of the circuit can be used to implement fault tolerance at low hardware-overhead costs.
[1] Z. Barzilaiet al., "Accurate fault modeling and efficient simulation of differential CVS circuits," inProc. IEEE Int. Test Conf., 1985, pp. 722-729.
[2] K.M. Chu and D.L. Pulfrey, "Design procedures for differential cascode voltage switch circuits,"IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1082-1087, Dec. 1986.
[3] C.K. Erdelyiet al., "Cascode voltage switch logic design,"VLSI Design, pp. 78-86, Oct. 1984.
[4] L.G. Helleret al., "Cascode voltage switch logic: A differential CMOS logic family," inProc. IEEE Int. Solid-State Circuits Conf., 1984, pp. 16-17.
[5] P. N. Marinos, "Differential cascode voltage switch logic circuits," Tech. Rep., Dep. Elec. Eng., Duke Univ., Durham, NC 27706, June 1986.
[6] N. Kanopoulos and N. Vasanthavada, "Testing of differential cascode voltage switch (DCVS) circuits,"IEEE J. Solid-State Circuits, vol. SC-25, no. 3, pp. 806-813, June 1990.
[7] F. P. Mathur and A. Avizienis, "Reliability analysis and architecture of a hybrid redundant digital system: Generalized triple modular redundancy with self-repair," inProc. AFIPS Spring Joint Comput. Conf., 1970, pp. 375-383.
[8] HSPICE User's Manual. Meta-Software, Inc., 1985.

