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A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay
July 1992 (vol. 41 no. 7)
pp. 881-886

An efficient technique for designing a totally self-checking checker for 1/n code (n<3) with minimum possible gate delay is proposed. The checker consists of a 1/n to k/2k translator and a k/2k code checker. The translator is implemented using a NOR array and checker using a NOR-NOR PLA. The design technique is applicable for all but a few values of n. It has been shown that the checkers constructed using the proposed technique occupy minimum or near-minimum chip area depending on the value of n. This new technique also has the advantage over existing ones in terms of speed or hardware.

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Index Terms:
totally self-checking checker; 1-out-of-N code; minimum gate delay; translator; NOR array; NOR-NOR PLA; delays; error detection codes; fault tolerant computing; logic arrays; logic design; logic testing.
Citation:
D.L. Tao, C.R.P. Hartmann, P.K. Lala, "A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay," IEEE Transactions on Computers, vol. 41, no. 7, pp. 881-886, July 1992, doi:10.1109/12.256456
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