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D.L. Tao, C.R.P. Hartmann, P.K. Lala, "A General Technique for Designing Totally SelfChecking Checker for 1outofN Code with Minimum Gate Delay," IEEE Transactions on Computers, vol. 41, no. 7, pp. 881886, July, 1992.  
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@article{ 10.1109/12.256456, author = {D.L. Tao and C.R.P. Hartmann and P.K. Lala}, title = {A General Technique for Designing Totally SelfChecking Checker for 1outofN Code with Minimum Gate Delay}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {7}, issn = {00189340}, year = {1992}, pages = {881886}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.256456}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  A General Technique for Designing Totally SelfChecking Checker for 1outofN Code with Minimum Gate Delay IS  7 SN  00189340 SP881 EP886 EPD  881886 A1  D.L. Tao, A1  C.R.P. Hartmann, A1  P.K. Lala, PY  1992 KW  totally selfchecking checker; 1outofN code; minimum gate delay; translator; NOR array; NORNOR PLA; delays; error detection codes; fault tolerant computing; logic arrays; logic design; logic testing. VL  41 JA  IEEE Transactions on Computers ER   
An efficient technique for designing a totally selfchecking checker for 1/n code (n<3) with minimum possible gate delay is proposed. The checker consists of a 1/n to k/2k translator and a k/2k code checker. The translator is implemented using a NOR array and checker using a NORNOR PLA. The design technique is applicable for all but a few values of n. It has been shown that the checkers constructed using the proposed technique occupy minimum or nearminimum chip area depending on the value of n. This new technique also has the advantage over existing ones in terms of speed or hardware.
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