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Performance of Synchronous and Asynchronous Schemes for VLSI Systems
July 1992 (vol. 41 no. 7)
pp. 858-872

Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed.

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Index Terms:
synchronous schemes; asynchronous schemes; VLSI systems; homogeneous technology; interconnections; gates; synchronizers; delay models; time performances; circuit CAD; computer architecture; delays; performance evaluation; VLSI.
Citation:
M. Afghahi, C. Svensson, "Performance of Synchronous and Asynchronous Schemes for VLSI Systems," IEEE Transactions on Computers, vol. 41, no. 7, pp. 858-872, July 1992, doi:10.1109/12.256454
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