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| J.R.S. Blair, E.L. Lloyd, "Minimizing External Wires in Generalized Single-Row Routing," IEEE Transactions on Computers, vol. 41, no. 6, pp. 771-776, June, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/12.144629, author = {J.R.S. Blair and E.L. Lloyd}, title = {Minimizing External Wires in Generalized Single-Row Routing}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {6}, issn = {0018-9340}, year = {1992}, pages = {771-776}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.144629}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Minimizing External Wires in Generalized Single-Row Routing IS - 6 SN - 0018-9340 SP771 EP776 EPD - 771-776 A1 - J.R.S. Blair, A1 - E.L. Lloyd, PY - 1992 KW - external wires; single-row routing; automated design; VLSI chips; circuit layout CAD; VLSI. VL - 41 JA - IEEE Transactions on Computers ER - | |||
Much of the recent work on the automated design of VLSI chips has concentrated on routing problems associated with such designs. One major class of routing problems focuses on single-row routing. Recently, the traditional single-row routing model has been generalized to allow external wires. Under this generalized model, it is possible to route many more single-row routing instances than in the traditional model. There is, however, a clear disadvantage in the use of external wires, since they force a lengthening of the channels surrounding the single row of terminals. Thus, it is desirable for these generalized single-row routings to use a minimum number of external wires. A linear-time algorithm for determining the minimum number of external wires needed to route a given instance of single-row routing is provided here.
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