
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
A.K. Ramani, P.K. Chande, P.C. Sharma, "A General Model for Performance Investigations of Priority Based Multiprocessor System," IEEE Transactions on Computers, vol. 41, no. 6, pp. 747754, June, 1992.  
BibTex  x  
@article{ 10.1109/12.144626, author = {A.K. Ramani and P.K. Chande and P.C. Sharma}, title = {A General Model for Performance Investigations of Priority Based Multiprocessor System}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {6}, issn = {00189340}, year = {1992}, pages = {747754}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.144626}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A General Model for Performance Investigations of Priority Based Multiprocessor System IS  6 SN  00189340 SP747 EP754 EPD  747754 A1  A.K. Ramani, A1  P.K. Chande, A1  P.C. Sharma, PY  1992 KW  discrete time semiMarkov model; task priorities; system performance; multiprocessor system; crossbar interconnection network; performance measures; task scheduling; load balancing; performance optimization; Markov processes; multiprocessing systems; multiprocessor interconnection networks; performance evaluation. VL  41 JA  IEEE Transactions on Computers ER   
A general discrete time semiMarkov model is developed to investigate the effects of task priorities on the system performance of a multiprocessor system with crossbar interconnection network. The number of priority levels associated with the tasks in the system, connection times of different priority level requests, interrequest time, number of processing elements, and the number of shared resources are the parameters involved in estimation of the performance of the system. The bandwidth, queue length at a memory, waiting time for requests at different priority levels, and processor utilization are the performance measures quantified from the analysis. The results reveal the advantage received by the tasks at higher priority levels and the starvation experienced by the lower priority tasks. This information should be useful in the realtime task scheduling, load balancing, and performance optimization. The results obtained are validated with simulation.
[1] F. Ozguner and M. L. Kao, "A multiprocessor system for faulttolerant control of an articulated mechanism,"IEEE Trans. Indust. Electron., vol. IE31, pp. 130136, May 1984.
[2] A. Gupta and H. M. Toong, "Microcomputers in industrial control applications,"IEEE Trans. Indust. Elect., vol. IE31, pp. 109119, May 1984.
[3] P. K. Chande, A. K. Ramani, and P. C. Sharma, "Modular TMR multiprocessor system,"IEEE Trans. Indust. Electron., Feb. 1989.
[4] R. A. Finkel and M. H. Solomon, "Processors interconnections strategies,"IEEE Trans. Comput., vol. C29, pp. 360371, May 1980.
[5] Special Issue on Interconnection Networks,IEEE Comput. Mag., vol. C14, Dec. 1981.
[6] H. D. Kirswann and F. Kaufmann, "Poolpopool of processors for process control applications,"IEEE Trans. Comput., vol. C33, pp. 869878, Oct. 1984.
[7] A. Gupta and HM. D. Toong, "Increasing throughput in multiprocessor system,"IEEE Trans. Indust. Electron., vol. IE32, Aug. 1985.
[8] K. M. Chandy and C. H. Sauer, "Approximate methods for analysis of queueing network models of computer system,"Comput. Surveys, vol. 10, pp. 263280, 1978.
[9] K. M. Chandy and C. H. Sauer, "Computational methods for product form queueing networks,"Commun. ACM, vol. 23, pp. 573583, 1980.
[10] D. P. Bhandarkar, "Analysis of memory interference in multiprocessor,"IEEE Trans. Comput., vol. C24, pp. 897908, Sept. 1975.
[11] C. H. Hoogendoorn, "A general form memory interference in multiprocessor,"IEEE Trans. Comput., vol. C26, pp. 9981005, Oct. 1977.
[12] J. P. Buzen, "Computational algorithms for closed queueing networks with exponential servers,"Commun. ACM, vol. 16, no. 9, Sept. 1973.
[13] J. W. McCredie, "Analytic models as aids in multiprocessor design," inProc. 7th Annu. Princeton Conf., Inf. Sci. and Syst., Mar. 1973, pp. 186191.
[14] T. E. Roberts and B. W. Johnson, "A fault tolerant multiprocessor for realtime control applications," inProc. IEEE 1987 Indust. Electron. Conf., IECON '87, Nov. 1987, pp. 512517.
[15] B. Pappasratorn and P. Prapinmongkolkarn, "A small scale distributed multimicroprocessor system using shared memory techniques,"IEEE Trans. Indust. Electron., vol. IE32, pp. 97102, May 1985.
[16] W. A. Wolf and C. G. Bell, "C. mmpA multiprocessor," inProc. Fall Joint Comput. Conf., AFIPS, 1972, pp. 756777.
[17] M. Ajmare and M. Gerla, "Markov models for multiple bus multiprocessor system," Tech. Rep. CSD 810304, U.C.L.A., Los Angeles, CA, Feb. 1981.
[18] K. Jovan and Miodrag P., "A multilevel microcomputer structured system for supervisory monitoring," inProc. IEEE 1987 Indust. Electron. Conf., IECON '87, Nov. 1987, pp. 512517.
[19] W. S. Holderby, "Maintainability considerations in a fault tolerant / fault proofsystems design,"IEEE Trans. Ind. Electron., vol. IE31, no. 2., pp. 120129, May 1984.
[20] K. S. Trivedi,Probability and Statistics with Reliability, Queueing and Computer Science Applications. Englewood Cliffs, NJ: PrenticeHall, 1982.
[21] P. Heidelberger and S. S. Lavenberg, "Computer performance evaluation methodology,"IEEE Trans. Comput., vol. C33, Dec. 1984.
[22] T. N. Mudge and H. B. AlSadourn, "Memory interference models with variable connection time,"IEEE Trans. Comput., vol. C33, pp. 10331038, Nov. 1984.
[23] T. N. Mudge and H. B. AlSadoun, "A semiMarkov model for the performance of multiplebus systems,"IEEE Trans. Comput., vol. C34, pp. 934942, Oct. 1985.
[24] T. Lang, M. Valcro, and I. Alegre, "Bandwidth of crossbar and multiplebus connections for multiprocessors,"IEEE Trans. Comput., vol. C31, pp. 12271233, Dec. 1982.
[25] D. Locke, E. D. Jensen, and H. Tokuda, "A time driven scheduling model for realtime operating system," inProc. Advanced Workshop FaultTolerant Comput., ISROIISc., Bangalore, India, July 1987.
[26] H. S. Stone,Introduction to Computer Architecture. Chicago, Science Research Associates, Inc.
[27] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGrawHill, 1984.
[28] L. Ciminiera and A. Valenzano, "Acknowledgment and priority mechanisms in IEEE 802.4 token bus,"IEEE Trans. Industrial Electron., vol. IE35, no. 2, May 1988.
[29] P. H. Enslow, "Multiprocessor organization,"Comput. Surveys, ACM, vol. 9, pp. 103109, Mar. 1977.
[30] B. H. Humond, "A study in memory interference models," Ph.D dissertation, Computing Research Lab., University of Michigan, Ann Arbor, Apr. 1985.
[31] S. M. Ross,Applied Probabilily Models with Optimization Applications. San Francisco, CA: HoldenDay 1970.
[32] S. M. Ross,Stochastic Processes. New York: Wiley, 1983, pp. 205207.
[33] N. Bogunovic, "Process scheduling procedure for a class of realtime computer system,"IEEE Trans. Indust. Electron., vol. IE34, pp. 2934, Feb. 1987.
[34] K. Schwan, T. Bihari, B. W. Weide, and G. Taulbee, "Highperformance operating system primitives for robotics and realtime control systems,"ACM Trans. Comput. Syst., vol. 5, no. 3, pp. 189231, Aug. 1987.