This Article 
 Bibliographic References 
 Add to: 
A General Model for Performance Investigations of Priority Based Multiprocessor System
June 1992 (vol. 41 no. 6)
pp. 747-754

A general discrete time semi-Markov model is developed to investigate the effects of task priorities on the system performance of a multiprocessor system with crossbar interconnection network. The number of priority levels associated with the tasks in the system, connection times of different priority level requests, interrequest time, number of processing elements, and the number of shared resources are the parameters involved in estimation of the performance of the system. The bandwidth, queue length at a memory, waiting time for requests at different priority levels, and processor utilization are the performance measures quantified from the analysis. The results reveal the advantage received by the tasks at higher priority levels and the starvation experienced by the lower priority tasks. This information should be useful in the real-time task scheduling, load balancing, and performance optimization. The results obtained are validated with simulation.

[1] F. Ozguner and M. L. Kao, "A multiprocessor system for fault-tolerant control of an articulated mechanism,"IEEE Trans. Indust. Electron., vol. IE-31, pp. 130-136, May 1984.
[2] A. Gupta and H. M. Toong, "Microcomputers in industrial control applications,"IEEE Trans. Indust. Elect., vol. IE-31, pp. 109-119, May 1984.
[3] P. K. Chande, A. K. Ramani, and P. C. Sharma, "Modular TMR multiprocessor system,"IEEE Trans. Indust. Electron., Feb. 1989.
[4] R. A. Finkel and M. H. Solomon, "Processors interconnections strategies,"IEEE Trans. Comput., vol. C-29, pp. 360-371, May 1980.
[5] Special Issue on Interconnection Networks,IEEE Comput. Mag., vol. C-14, Dec. 1981.
[6] H. D. Kirswann and F. Kaufmann, "Poolpo-pool of processors for process control applications,"IEEE Trans. Comput., vol. C-33, pp. 869-878, Oct. 1984.
[7] A. Gupta and H-M. D. Toong, "Increasing throughput in multiprocessor system,"IEEE Trans. Indust. Electron., vol. IE-32, Aug. 1985.
[8] K. M. Chandy and C. H. Sauer, "Approximate methods for analysis of queueing network models of computer system,"Comput. Surveys, vol. 10, pp. 263-280, 1978.
[9] K. M. Chandy and C. H. Sauer, "Computational methods for product form queueing networks,"Commun. ACM, vol. 23, pp. 573-583, 1980.
[10] D. P. Bhandarkar, "Analysis of memory interference in multiprocessor,"IEEE Trans. Comput., vol. C-24, pp. 897-908, Sept. 1975.
[11] C. H. Hoogendoorn, "A general form memory interference in multiprocessor,"IEEE Trans. Comput., vol. C-26, pp. 998-1005, Oct. 1977.
[12] J. P. Buzen, "Computational algorithms for closed queueing networks with exponential servers,"Commun. ACM, vol. 16, no. 9, Sept. 1973.
[13] J. W. McCredie, "Analytic models as aids in multiprocessor design," inProc. 7th Annu. Princeton Conf., Inf. Sci. and Syst., Mar. 1973, pp. 186-191.
[14] T. E. Roberts and B. W. Johnson, "A fault tolerant multiprocessor for real-time control applications," inProc. IEEE 1987 Indust. Electron. Conf., IECON '87, Nov. 1987, pp. 512-517.
[15] B. Pappasratorn and P. Prapinmongkolkarn, "A small scale distributed multi-microprocessor system using shared memory techniques,"IEEE Trans. Indust. Electron., vol. IE-32, pp. 97-102, May 1985.
[16] W. A. Wolf and C. G. Bell, "C. mmp-A multiprocessor," inProc. Fall Joint Comput. Conf., AFIPS, 1972, pp. 756-777.
[17] M. Ajmare and M. Gerla, "Markov models for multiple bus multiprocessor system," Tech. Rep. CSD 810304, U.C.L.A., Los Angeles, CA, Feb. 1981.
[18] K. Jovan and Miodrag P., "A multilevel microcomputer structured system for supervisory monitoring," inProc. IEEE 1987 Indust. Electron. Conf., IECON '87, Nov. 1987, pp. 512-517.
[19] W. S. Holderby, "Maintainability considerations in a fault tolerant / fault proofsystems design,"IEEE Trans. Ind. Electron., vol. IE-31, no. 2., pp. 120-129, May 1984.
[20] K. S. Trivedi,Probability and Statistics with Reliability, Queueing and Computer Science Applications. Englewood Cliffs, NJ: Prentice-Hall, 1982.
[21] P. Heidelberger and S. S. Lavenberg, "Computer performance evaluation methodology,"IEEE Trans. Comput., vol. C-33, Dec. 1984.
[22] T. N. Mudge and H. B. Al-Sadourn, "Memory interference models with variable connection time,"IEEE Trans. Comput., vol. C-33, pp. 1033-1038, Nov. 1984.
[23] T. N. Mudge and H. B. Al-Sadoun, "A semi-Markov model for the performance of multiple-bus systems,"IEEE Trans. Comput., vol. C-34, pp. 934-942, Oct. 1985.
[24] T. Lang, M. Valcro, and I. Alegre, "Bandwidth of cross-bar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1227-1233, Dec. 1982.
[25] D. Locke, E. D. Jensen, and H. Tokuda, "A time driven scheduling model for real-time operating system," inProc. Advanced Workshop Fault-Tolerant Comput., ISRO-IISc., Bangalore, India, July 1987.
[26] H. S. Stone,Introduction to Computer Architecture. Chicago, Science Research Associates, Inc.
[27] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
[28] L. Ciminiera and A. Valenzano, "Acknowledgment and priority mechanisms in IEEE 802.4 token bus,"IEEE Trans. Industrial Electron., vol. IE-35, no. 2, May 1988.
[29] P. H. Enslow, "Multiprocessor organization,"Comput. Surveys, ACM, vol. 9, pp. 103-109, Mar. 1977.
[30] B. H. Humond, "A study in memory interference models," Ph.D dissertation, Computing Research Lab., University of Michigan, Ann Arbor, Apr. 1985.
[31] S. M. Ross,Applied Probabilily Models with Optimization Applications. San Francisco, CA: Holden-Day 1970.
[32] S. M. Ross,Stochastic Processes. New York: Wiley, 1983, pp. 205-207.
[33] N. Bogunovic, "Process scheduling procedure for a class of real-time computer system,"IEEE Trans. Indust. Electron., vol. IE-34, pp. 29-34, Feb. 1987.
[34] K. Schwan, T. Bihari, B. W. Weide, and G. Taulbee, "High-performance operating system primitives for robotics and real-time control systems,"ACM Trans. Comput. Syst., vol. 5, no. 3, pp. 189-231, Aug. 1987.

Index Terms:
discrete time semi-Markov model; task priorities; system performance; multiprocessor system; crossbar interconnection network; performance measures; task scheduling; load balancing; performance optimization; Markov processes; multiprocessing systems; multiprocessor interconnection networks; performance evaluation.
A.K. Ramani, P.K. Chande, P.C. Sharma, "A General Model for Performance Investigations of Priority Based Multiprocessor System," IEEE Transactions on Computers, vol. 41, no. 6, pp. 747-754, June 1992, doi:10.1109/12.144626
Usage of this product signifies your acceptance of the Terms of Use.