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K.P. Belkhale, P. Banerjee, "Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor," IEEE Transactions on Computers, vol. 41, no. 6, pp. 699709, June, 1992.  
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@article{ 10.1109/12.144622, author = {K.P. Belkhale and P. Banerjee}, title = {Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {6}, issn = {00189340}, year = {1992}, pages = {699709}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.144622}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor IS  6 SN  00189340 SP699 EP709 EPD  699709 A1  K.P. Belkhale, A1  P. Banerjee, PY  1992 KW  parallel algorithms; hypercube multiprocessor; geometric connected component labeling; merging problem; run time; memory requirements; complexity; computational geometry; hypercube networks; parallel algorithms. VL  41 JA  IEEE Transactions on Computers ER   
Parallel algorithms for the geometric connected component labeling (GCCL) problem on a hypercube multiprocessor can be designed by dividing the domain, consisting of a number of rectangles, into regions using a slice or rectangular partitioning scheme. Each processor in the hypercube is assigned one partition. The processor determines the connected sets of rectangles in its partition. The connected sets at different processors have to then be combined across processors into globally connected sets. This merging problem is defined as the GCCL problem. Different algorithms for the GCCL problem are presented. Each of the algorithms involves d stages of message passing, for a ddimensional hypercube. The basic idea in these algorithms is that in each stage a processor increases its knowledge of the domain. The algorithms described in this paper differ in their run time, memory requirements, and message complexity. These algorithms have been implemented on an Intel iPSC2/D4/MX hypercube.
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