This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The Total Delay Fault Model and Statistical Delay Fault Coverage
June 1992 (vol. 41 no. 6)
pp. 688-698

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed.

[1] E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas, and W. T. Davis, "Delay test generation," inProc. 14th Design Automat. Conf., 1977, pp. 486-491.
[2] J. D. Lesser and J. J. Schedletsky, "An experimental delay test generator for LSI,"IEEE Trans. Comput., vol. C-29, no. 3, pp. 235-248, 1980.
[3] C. J. Lin and S. M. Reddy, "On delay testing in logic circuits,"IEEE Trans. Comput.-Aided Design, vol. CAD-6, no. 5, pp. 694-703, 1987.
[4] E. S. Park and M. R. Mercer, "Robust and nonrobust tests for path delay faults in a combinational circuit," inProc. 1987 Int. Test Conf., 1987, pp. 1027-1034.
[5] J. Savir and W. H. McAnney, "Random pattern testability of delay faults," inProc. 1986 Int. Test Conf., 1986, pp. 263-273.
[6] G. L. Smith, "Model for delay faults based upon path," inProc. 1985 Int. Test Conf., 1985, pp. 342-349.
[7] M. Keating, "Fundamental limits to timing accuracy," inProc. 1986 Int. Test Conf., 1986, pp. 756-762.
[8] J. S. Pabst, "Timing accuracy and yield estimation," inProc. 1986 Int. Test Conf., 1986, pp. 778-787.
[9] D. M. Wu, C. E. Radke, and J. P. Roth, "Statistical AC test coverage," inProc. 1986 Int. Test Conf., 1986, pp. 538-541.
[10] J. L. Carter, V. S. Iyengar, and B. K. Rosen, "Efficient test coverage determination for delay faults," inProc. 1987 Int. Test Conf., 1987, pp. 418-428.
[11] E. S. Park and M. R. Mercer, "An efficient delay test generation system for combinational logic circuits," inProc. 27th Design Automat. Conf., 1989, pp. 522-528.
[12] A. Papoulis,Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, 1965.
[13] R. B. Hitchcock, G. L. Smith, and D. C. Cheng, "Timing analysis of computer hardware,"IBM J. Res. Develop., vol. 26, no. 1, pp. 100-105, 1982.
[14] J. H. Shelly and D. R. Tryon, "Statistical techniques of timing verification," inProc. 20th Design Automat. Conf., 1983, pp. 396-402.
[15] N. N. Tendolkar, "Analysis of timing failures due to random AC defects in VLSI modules," inProc. 22nd Design Automat. Conf., 1985, pp. 709-714.
[16] D. S. Cleverley, "The role of testing in achieving zero defects," inProc. 1983 Int. Test. Conf., 1983, pp. 248-253.
[17] V. S. Iyengar, B. K. Rosen, and I. Spillinger, "Delay test generation 1--Concepts and coverage metrics," inProc. Int. Test Conf., 1988, pp. 857-866.
[18] K. E. Torku and C. E. Radke, "Quality level and fault coverage for multichip modules," inProc. 20th Design Automat. Conf., 1983, pp. 201-206.
[19] R. L. Wadsack, "Fault coverage in digital integrated circuits,"Bell Syst. Tech. J., vol. 57, pp. 1475-1488, 1978.
[20] T. W. Williams and N. C. Brown, "Defect level as a function of fault coverage,"IEEE Trans. Comput., vol. C-30, no. 12, pp. 987-988, 1981.
[21] Y. Levendel and P. R. Menon, "Transition faults in combinational circuits: Input transition test generation and fault simulation," inProc. 1986 Fault Tolerant Comput. Symp., 1986, pp. 278-283.

Index Terms:
delay fault model; delay fault coverage; delay testing; statistical delay fault coverage; defect level model; delay faults; logic testing.
Citation:
E.S. Park, M.R. Mercer, T.W. Williams, "The Total Delay Fault Model and Statistical Delay Fault Coverage," IEEE Transactions on Computers, vol. 41, no. 6, pp. 688-698, June 1992, doi:10.1109/12.144621
Usage of this product signifies your acceptance of the Terms of Use.