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Cache Memories for Data Flow Machines
June 1992 (vol. 41 no. 6)
pp. 677-687

Cache memories for dataflow machines are presented, and, in particular, four design principles for reducing the working set size of dataflow caches are introduced. They are (1) controlling the number of active state processes, (2) optimizing instruction addresses, (3) using a block-structured operand matching/waiting memory, and (4) making deterministic replacements. Based on these principles, instruction and operand caches are organized. A bypass control is also devised that enables cache block replacement to overlap with normal cache access. Miss ratio and performance of the caches are evaluated on a register transfer level simulator of a dataflow machine. The results show that the instruction cache of 1 k words and the operand cache of 2 k words achieve sufficiently low miss ratios. The bypass control compensates for the bandwidth of a narrow swapping channel to the extent that about eight dataflow processors with the caches can be integrated in an LSI chip.

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Index Terms:
cache memories; data flow machines; dataflow caches; cache block replacement; register transfer level simulator; buffer storage; memory architecture.
Citation:
M. Takesue, "Cache Memories for Data Flow Machines," IEEE Transactions on Computers, vol. 41, no. 6, pp. 677-687, June 1992, doi:10.1109/12.144620
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