Issue No.05 - May (1992 vol.41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.142692
<p>The concept of k-UCP circuits is proposed. In a k-UCP circuit, all stuck-at faults and stuck-open faults can be detected and located by k+1 and k(k+1)+1 tests, respectively, under the highly observable condition. A method of modifying an arbitrary combinational circuit into a k-UCP circuit is also proposed.</p>
testable design; logic circuits; highly observable condition; stuck-at faults; stuck-open faults; combinational circuit; combinatorial circuits; fault tolerant computing; integrated circuit testing; integrated logic circuits; logic testing.
W. Xiaoqing, K. Kinoshita, "A Testable Design of Logic Circuits Under Highly Observable Condition", IEEE Transactions on Computers, vol.41, no. 5, pp. 654-659, May 1992, doi:10.1109/12.142692