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An Effective BIST Scheme for ROM's
May 1992 (vol. 41 no. 5)
pp. 646-653

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR.

[1] Y. Zorian and A. Ivanov, "EEODM: An Effective BIST scheme for ROMs," inProc. Int. Test Conf., Washington, DC, Sept. 1990, pp. 871-879.
[2] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.
[3] R. Truer, H. Fujiwara, and V. K. Agarwal, "Implementing a built-in self-test PLA design,"IEEE Design Test Comput., vol. 2, no. 2, pp. 37-48, Apr. 1985.
[4] S. K. Jain and C. H. Stroud, "Built-in self-testing of embedded memories,"IEEE Design Test Comput., vol. 3, no. 5, pp. 27-37, Oct. 1986.
[5] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal, "Serial interfacing for embedded-memory testing,"IEEE Design Test Comput., vol. 7, no. 2, pp. 52-63, Apr. 1990.
[6] Y. Zorian, "A structured approach to macrocell testing using built-in self-test," inProc. IEEE Custom Integrated Circuits Conf., May 1990, pp. 28.3.1-28.3.4.
[7] S. Waser, "What is necessary for testing ROM's and PROMS?," inProc. IEEE Semiconductor Test Symp., Oct. 1974, pp. 87- 113.
[8] H. Thaler, "Pattern verification and address sequence sensitivity of ROM's by signature testing," inProc. IEEE Semiconductor Test Symp., Oct. 1978, pp. 84-85.
[9] A. J. van de Goor,Testing Semiconductor Memories: Theory and Practice, Chichester, England: Wiley, Sept. 1990.
[10] Y. Zorian and V. K. Agarwal, "A general scheme to optimize error masking in built-in self-testing," inProc. 18th Int. Symp. Fault-Tolerant Comput., Vienna, Austria, July 1986, pp. 410-415.
[11] E. J. McCluskey, "Verification testing--A pseudoexhaustive test technique,"IEEE Trans. Comput., vol. C-33, pp. 265-272, June 1984.
[12] R. A. Frohwerk, "Signature analysis: A new digital field service method,"Hewlett-Packard J., pp. 2-8, May 1977.
[13] T. Sridhar, D. S. Ho, T. J. Powell, and S. M. Thatte, "Analysis and simulation of parallel signature analyzers," inProc. Int. Test Conf., Nov. 1982, pp 656-661.
[14] A. Miczo,Digital Logic Testing and Simulation. New York: Harper and Row, 1986.
[15] B.W. Johnson,Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, Reading, Mass., 1989.
[16] D. P. Siewiorek, and R. S. Swarz,The Theory and Practice of Reliable System Design, Bedford, MA: Digital, 1982.
[17] N. Saxena and E. J. McCluskey, "Extended precision checksums," inProc. Int. Symp. Fault-Tolerant Comput., June 1987, pp. 142-147.
[18] N. Saxena and E. J. McCluskey, "Arithmetic and Galois checksums," inProc. IEEE Int. Conf. Comput.-Aided Design, Nov. 1989, pp. 570-573.
[19] J. Kuban and W. Bruce, "The MC6804P2 built-in self-test," inProc. IEEE Int. Test Conf., Oct. 1983, pp. 295-300.
[20] S. M. Reddy, K. K. Saluja, and M. Karpovsky, "A data compression technique for built-in self-test,"IEEE Trans. Comput., vol. 37, pp. 1151-1156, Sept. 1988.
[21] Y. Zorian, "Optimizing error coverage in built-in self-test by output data modification," Ph.D. dissertation, Elec. Eng. Dep., McGill Univ., Montreal, Canada, Sept. 1987.
[22] Y. Zorian and V. K. Agarwal, "Optimizing error masking in BIST by output data modification,"J. Electron. Testing: Theory and Appl., vol. 1, no.1, pp. 72-79, Feb. 1990.
[23] S. Z. Hassan, D. J. Lu, and E. J. McCluskey, "Parallel signature analyzers--Detection capability and extensions," inProc. Spring Compcon, 1983, pp. 440-445.
[24] J. Savir, "The bidirectional double latch,"IEEE Trans. Comput., vol. C-35, pp. 65-66, Jan. 1986.
[25] W. H. McAnney and J. Savir, "Built-in checking of the correct self-test signature,"IEEE Trans. Comput., vol. C-37, pp. 1142-1145, Sept. 1988.
[26] Y. Nozuyama, A. Nishimura, and J. Iwamura, "Implementation and evaluation of microinstruction controlled self-test using a masked microinstruction scheme," inProc. Int. Test Conf., Washington, DC, Aug. 1989, pp. 624-632.
[27] Th. M. Schwair and H. C. Ritter, "Complete self-test architecture for a coprocessor," inProc. Int. Test Conf., Washington, DC, Aug. 1990, pp. 886-890.
[28] P. Nagvajara and M. G. Karpovsky, "Built-in self-diagnostic read-only memories" inProc. Int. Test Conf., Nashville, TN, Oct. 1991, pp. 695-703.
[29] Y. Zorian, "Built-in self-test technique for read-only memories," U.S. Patent 5091 908.

Index Terms:
linear space compaction; BIST; built-in self-test; ROMs; fault coverage; error escape; aliasing; test generation; exhaustive test; output data evaluation; multiple-input linear feedback shift register; time compaction; nonlinear compaction; data modification; bidirectional MISR; built-in self test; integrated circuit testing; read-only storage.
Y. Zorian, A. Ivanov, "An Effective BIST Scheme for ROM's," IEEE Transactions on Computers, vol. 41, no. 5, pp. 646-653, May 1992, doi:10.1109/12.142691
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