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Fast Algorithms for Routing Around Faults in Multibutterflies and Randomly-Wired Splitter Networks
May 1992 (vol. 41 no. 5)
pp. 578-587

Simple deterministic O(log N)-step algorithms for routing permutations of packets in multibutterflies and randomly wired splitter networks are described. The algorithms are robust against faults (even in the worst case), and are efficient from a practical point of view. As a consequence, it is found that the multibutterfly is an excellent candidate for a high-bandwidth low-diameter switching network underlying a shared-memory machine.

[1] M. Ajtai, J. Komlos, and E. Szemeredi, "AnO(nlogn) sorting network,"Combinatorica, vol. 3, pp. 1-19, 1983.
[2] S. Arora, T. Leighton, and B. Maggs, "On-line algorithms for path selection in a nonblocking network," inProc. 22nd Annu. ACM Symp. Theory Comput., May 1990, pp. 149-158.
[3] L. A. Bassalygo and M. S. Pinsker, "Complexity of an optimum nonblocking switching network without reconnections,"Problems Inform. Transmission, vol. 9, pp. 64-66, 1974.
[4] F. Chong, E. Egozy, and A. DeHon, "Fault tolerance and performance of multipath multistage interconnection networks," inAdvanced Research in VLSI: Proc. MIT/Brown Conf. 1992, T. F. Knight, Jr. and J. Savage, Eds. Cambridge, MA: MIT Press, Mar. 1992, to be published.
[5] A. DeHon, T. Knight, and H. Minsky, "Fault-tolerant design for multi-stage routing networks," inProc. Int. Symp. Shared Memory Multiprocessing, Inform. Processing Soc. of Japan, Apr. 1991.
[6] C. Dwork, D. Peleg, N. Pippenger, and E. Upfal, "Byzantine agreement in faulty networks,"SIAM J. Comput., vol. 17, no. 5, pp. 975-988, 1988.
[7] S. E. Fahlman, "The hashnet interconnection scheme," Tech. Rep. CMU-CS-80-125, Dep. Comput. Sci., Carnegie-Mellon Univ., Pittsburgh, PA, June 1980.
[8] J. Friedman and N. Pippenger, "Expanding graphs contain all small trees,"Combinatorica, vol. 7, no. 1, pp. 71-76, 1987.
[9] A. V. Goldberg, S. A. Plotkin, and B. M. Maggs, "A parallel algorithm for reconfiguring a multibutterfly network with faults," unpublished manuscript, Dec. 1991.
[10] J. Hastad, T. Leighton, and M. Newman, "Fast computation using faulty hypercubes," inProc. 21st Annu. ACM Symp. Theory Comput., May 1989, pp. 251-263.
[11] N. Kahale, "Better expansion for ramanujan graphs," inProc. 32nd Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 1991, pp. 398-404.
[12] C. Kaklamanis, A. R. Karlin, F. T. Leighton, V. Milenkovic, P. Raghavan, S. Rao, C. Thomborson, and A. Tsantilas, "Asymptotically tight bounds for computing with faulty arrays of processors," inProc. 31st Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 1990, pp. 285-296.
[13] T. F. Knight, Jr., "Technologies for low latency interconnection switches," inProc. 1989 ACM Symp. Parallel Algorithms and Architectures, June 1989, pp. 351-358.
[14] R. R. Koch, "Increasing the size of a network by a constant factor can increase performance by more than a constant factor," inProc. 29th Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 1988, pp. 221-230.
[15] S. Konstantinidou and E. Upfal, "Experimental comparison of multistage networks," IBM Almaden Research Center, unpublished manuscript, 1991.
[16] C. P. Kruskal and M. Snir, "The performance of multistage interconnection networks for multiprocessors,"IEEE Trans. Comput., vol. C-32, pp. 1091-1098, Dec. 1983.
[17] C. P. Kruskal and M. Snir, "A unified theory of interconnection network structure,"Theoret. comput. Sci., vol. 48, pp. 75-94, 1986.
[18] T. Leighton, "Tight bounds on the complexity of parallel sorting,"IEEE Trans. Comput., vol. C-34, no. 4, pp. 344-354, Apr. 1985.
[19] F. T. Leighton and B. M. Maggs, "Introduction to parallel algorithms and architectures: Expanders, PRAM's, VLSI," manuscript in preparation.
[20] T. Leighton, C. L. Leiserson, and M. Klugerman, "Theory of parallel and VLSI computation," Research Seminar Series Rep. MIT/LCS/RSS 10, MIT Lab. for Comput. Sci., May 1991.
[21] J. Lim,Two-Dimensional Signal and Image Processing. Englewood Cliffs, NJ: Prentice-Hall, 1990.
[22] C. E. Leiserson, "Fat-trees: Universal networks for hardware-efficient supercomputing,"IEEE Trans. Comput., vol. C-34, pp. 892-900, Oct. 1985.
[23] A. Lubotzky, R. Phillips, and P. Sarnak, "Ramanujan graphs,"Combinatorica, vol. 8, no. 3, pp. 261-277, 1988.
[24] S. K. Park and K. W. Miller, "Random number generators: Good ones are hard to find,"Commun. ACM, vol. 31, pp. 1192-1201, Oct. 1988.
[25] M. O. Rabin, "Efficient dispersal of information for security, load balancing, and fault tolerance,"J. ACM, vol. 36, no. 2, Apr. 1989.
[26] P. Raghavan, "Robust algorithms for packet routing in a mesh," inProc. 1989 ACM Symp. Parallel Algorithms and Architectures, June 1989, pp. 344-350.
[27] R. D. Rettberg, W. R. Crowther, P. P. Carvey, and R. S. Tomlinson, "The monarch parallel processor hardware design,"IEEE Comput. Mag., vol. 23, no. 4, pp. 18-30, Apr. 1990.
[28] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[29] E. Upfal, "AnO(logN) deterministic packet routing scheme," inProc. 21st Annu. ACM Symp. Theory Comput., May 1989, pp. 241-250.

Index Terms:
fault routing algorithms; deterministic; algorithms; packet permutations routing; multibutterflies; randomly-wired splitter networks; switching network; shared-memory machine; computational complexity; fault tolerant computing; multiprocessor interconnection networks.
F.T. Leighton, B.M. Maggs, "Fast Algorithms for Routing Around Faults in Multibutterflies and Randomly-Wired Splitter Networks," IEEE Transactions on Computers, vol. 41, no. 5, pp. 578-587, May 1992, doi:10.1109/12.142684
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