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D.L. Lee, "Architecture of an Array Processor Using a Nonlinear Skewing Scheme," IEEE Transactions on Computers, vol. 41, no. 4, pp. 499505, April, 1992.  
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@article{ 10.1109/12.135554, author = {D.L. Lee}, title = {Architecture of an Array Processor Using a Nonlinear Skewing Scheme}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {4}, issn = {00189340}, year = {1992}, pages = {499505}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.135554}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Architecture of an Array Processor Using a Nonlinear Skewing Scheme IS  4 SN  00189340 SP499 EP505 EPD  499505 A1  D.L. Lee, PY  1992 KW  array processor; nonlinear skewing scheme; interconnection network; skewing schemes; array processor architecture; cellular arrays; multiprocessor interconnection networks; parallel architectures. VL  41 JA  IEEE Transactions on Computers ER   
The problem of constructing an array processor with N processing elements, N memories, and an interconnection network which provides conflictfree access and alignment of various Nvectors including rows, columns, diagonals, contiguous blocks, and distributed blocks of N*N arrays, where N is any even power of two, is discussed. The use of linear skewing schemes offers no solution to this problem. The solution developed makes use of a nonlinear skewing scheme. The solution leads to a simple, efficient array processor architecture. In particular, the memory organization requires O(log N) gates to generate memory addresses for any of the Nvectors simultaneously in O(1) time. The interconnection structure is able to accomplish data alignment for any of the Nvectors with a single pass through a network of O(N log N) gates. As the system uses the minimum number of memories, it allows both processing elements and memories to achieve the highest utilization possible.
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