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Architecture of an Array Processor Using a Nonlinear Skewing Scheme
April 1992 (vol. 41 no. 4)
pp. 499-505

The problem of constructing an array processor with N processing elements, N memories, and an interconnection network which provides conflict-free access and alignment of various N-vectors including rows, columns, diagonals, contiguous blocks, and distributed blocks of N*N arrays, where N is any even power of two, is discussed. The use of linear skewing schemes offers no solution to this problem. The solution developed makes use of a nonlinear skewing scheme. The solution leads to a simple, efficient array processor architecture. In particular, the memory organization requires O(log N) gates to generate memory addresses for any of the N-vectors simultaneously in O(1) time. The interconnection structure is able to accomplish data alignment for any of the N-vectors with a single pass through a network of O(N log N) gates. As the system uses the minimum number of memories, it allows both processing elements and memories to achieve the highest utilization possible.

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Index Terms:
array processor; nonlinear skewing scheme; interconnection network; skewing schemes; array processor architecture; cellular arrays; multiprocessor interconnection networks; parallel architectures.
Citation:
D.-L. Lee, "Architecture of an Array Processor Using a Nonlinear Skewing Scheme," IEEE Transactions on Computers, vol. 41, no. 4, pp. 499-505, April 1992, doi:10.1109/12.135554
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