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A.E. Barbour, "Solutions to the Minimization Problem of FaultTolerant Logic Circuits," IEEE Transactions on Computers, vol. 41, no. 4, pp. 429443, April, 1992.  
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@article{ 10.1109/12.135556, author = {A.E. Barbour}, title = {Solutions to the Minimization Problem of FaultTolerant Logic Circuits}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {4}, issn = {00189340}, year = {1992}, pages = {429443}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.135556}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Solutions to the Minimization Problem of FaultTolerant Logic Circuits IS  4 SN  00189340 SP429 EP443 EPD  429443 A1  A.E. Barbour, PY  1992 KW  logic circuits; optimization problem; faulttolerant circuits; gate minimization problem; fault tolerant computing; logic design; minimisation of switching nets. VL  41 JA  IEEE Transactions on Computers ER   
The optimization problem of a general approach for designing faulttolerant circuits is investigated. The gate minimization problem is solved so that optimal design with respect to the numbers of gates and levels is obtained. The concept and properties of block design are used to formulate, solve for, and construct the optimal form. The gate minimization problem for a faulttolerant circuit is formulated and a lower bound to the number of minimum gates for any design is established. For certain design parameters, explicit minimum solutions are given. When no minimum solution is found, sets of explicit block designs which produce nearminimum designs are characterized. In both cases, minimum and nearminimum algorithms which generate the blocks required to construct the logic for faulttolerant circuits in linear times are devised. If a block design does not have any connection with the minimum or nearminimum classes, an approximation algorithm which generates nearminimum blocks in a polynomial time is suggested.
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