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Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits
April 1992 (vol. 41 no. 4)
pp. 429-443

The optimization problem of a general approach for designing fault-tolerant circuits is investigated. The gate minimization problem is solved so that optimal design with respect to the numbers of gates and levels is obtained. The concept and properties of block design are used to formulate, solve for, and construct the optimal form. The gate minimization problem for a fault-tolerant circuit is formulated and a lower bound to the number of minimum gates for any design is established. For certain design parameters, explicit minimum solutions are given. When no minimum solution is found, sets of explicit block designs which produce near-minimum designs are characterized. In both cases, minimum and near-minimum algorithms which generate the blocks required to construct the logic for fault-tolerant circuits in linear times are devised. If a block design does not have any connection with the minimum or near-minimum classes, an approximation algorithm which generates near-minimum blocks in a polynomial time is suggested.

[1] R. Toeste, "Digital circuit redundancy,"IEEE Trans. Reliability, vol. R-13, pp. 42-61, 1964.
[2] F. P. Mathur and A. Avizienis, "Reliability analysis and architecture of a hybrid-redundant digital system: Generalized triple modular redundancy with self-repair," in1970 Spring Joint Computer Conf., AFIPS Conf. Proc., vol. 36, May 1970, pp. 375-383.
[3] S. E. Butuer, "A constructive approach to fault-tolerance in VLSI-based systems," inProc. 11th Annu. Int. Symp. Fault-Tolerant Comput., 1981, pp. 264-265.
[4] R. M. Geist and K. S. Trivedi, "Ultrahigh reliability prediction for fault-tolerant computer systems,"IEEE Trans. Comput., vol. C-32, pp. 1118-1127, Dec. 1983.
[5] W. G. Bouricius, W. C. Carter, D. C. Jessep, P. R. Schnaider, and A. B. Wadia, "Reliability modeling for fault-tolerant computers,"IEEE Trans. Comput., vol. C-20, pp. 1306-1311, Nov. 1971.
[6] In Depth Analysis of Leading Fault-Tolerant Computers, Datapro Research Corp. New York: McGraw-Hill, 1985.
[7] J. von Neumann, "Probabilistic logic and the synthesis of reliable organizms from unreliable components," inAutomata Studies, Ann. of Math. Studies, C. E. Shannon and J. McCarthy, Eds., no. 34. Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
[8] J. A. Abraham and D. P. Siewiorek, "An algorithm for the accurate reliability evaluation of triple modular redundancy networks,"IEEE Trans. Comput., vol. C-23, pp. 682-692, July 1974.
[9] D. P. Siewiorek and R. S. Swarz,The Theory and Practice of Reliable System Design. Bedford, MA: Digital Press, 1982.
[10] E. F. Moore and C. E. Shannon, "Reliable circuits using less reliable relays,"J. Franklin Instit., vol. 262, pp. 191-208 and 281-297, 1956.
[11] J. C. Tryon, "Quadded logic," inRedundancy Techniques for Computing System, W. C. Mann and R. H. Wilcox, Eds. Washington, DC: Spartan, 1962, pp. 205-228.
[12] W. H. Pierce,Failure-Tolerant Computer Design. New York: Academic, 1965.
[13] H. A. Freeman and G. Metze, "Fault-tolerant computers using dotted-logic redundancy techniques,"IEEE Trans. Comput., vol. C-21, pp. 867-871, Aug. 1972.
[14] D. K. Pradhan and S. M. Reddy, "Design of two-level fault-tolerant networks,"IEEE Trans. Comput., vol. C-23, pp. 41-48, Jan. 1974.
[15] T. E. Schwab and S. S. Yau, "An algebraic model of fault-masking logic circuits,"IEEE Trans. Comput., vol. C-32, pp. 809-825, Sept. 1983.
[16] P. J. Cameron and J. H. Van Lint,Graphs, Codes, and Designs, London Mathematical Society, Lecture Note Series 43. Cambridie, England: Cambridge University Press, 1980.
[17] A. E. Barbour, "A general theory of fault-tolerant design for digital systems," Ph.D. dissertation, Illinois Institute of Technology, Dec. 1985.
[18] A. E. Barbour and A. S. Wojcik, "A general, constructive approach to fault-tolerant design using redundancy,"IEEE Trans. Comput.vol. 38, pp. 15-29, Jan. 1989.
[19] A. E. Barbour, "Fault-tolerant logic design and block design theory," inProc. 31st Midwest Symp. Circuits and Systems, Marriott's Pavilion Hotel, St. Louis, MO, Aug. 9-12, 1988, pp. 976-979.
[20] J. A. Abraham, "A combinatorial solution to the reliability of interwoven redundant logic networks,"IEEE Trans. Comput., vol. C-24, pp. 578-584, May 1975.
[21] C. E. Stroud and A. E. Barbour, "Design for testability and test generation for static redundancy system level fault-tolerant circuits," inProc. IEEE Int. Test Conf., Washington DC, Aug. 29-31, 1989, pp. 812-818.
[22] C. E. Stroud and A. E. Barbour, "Reliability, testability, and yield of majority voting VLSI," in1990 ASIC Seminar and Exhibit, Rochester, NY, Sept. 17-21, 1990.
[23] E. J. McCluskey, "Minimization of Boolean functions,"Bell Syst. Tech. J., vol. 35, no. 6, pp. 1417-1444, Nov. 1956.
[24] P. Tison, "Generalization of consensus theory and application to the minimization of Boolean functions,"IEEE Trans. Electron. Comput., vol. EC-16, pp. 446-456, Aug. 1967.
[25] M-H. Young, "The minimal covering problem and automated design of two-level AND/OR optimal networks," UIUCDCS-R-79-966, Dep. Comput. Sci., Univ. of Ill. at Urbana-Champaign, Mar. 1979.
[26] K. P. Bogart,Introductory Combinatorics. Lonond, England: Pitman, 1983.

Index Terms:
logic circuits; optimization problem; fault-tolerant circuits; gate minimization problem; fault tolerant computing; logic design; minimisation of switching nets.
Citation:
A.E. Barbour, "Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits," IEEE Transactions on Computers, vol. 41, no. 4, pp. 429-443, April 1992, doi:10.1109/12.135556
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