This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Initializability Consideration in Sequential Machine Synthesis
March 1992 (vol. 41 no. 3)
pp. 374-379

It is shown that a finite-state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable (i.e. has synchronizing sequences). A fault simulator or a sequential circuit test generator that assumes all memory elements initially to be in the unknown state will be totally ineffective for such a design. Proper consideration for initializability during state assignment and logic optimization can guarantee the success for gate-level analysis tools. The conditions for initializability of finite-state machines are derived, and an automatic state assignment algorithm for logic minimality and initializability is given. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique, recommended for machines without a synchronizing sequence, is also discussed.

[1] G. De Micheliet al., "Optimal state assignment for finite state machines,"IEEE Trans. Comput.-Aided Design, vol. CAD-4, pp. 269-285, July 1985.
[2] S. Devadaset al., "MUSTANG: State assignment of finite state machines targeting multi-level logic implementations,"IEEE Trans. Comput-Aided Design, vol. CAD-7, pp. 1290-1300, Dec. 1988.
[3] R. Brayton, G. Hachtel, C. McMullen, and A. Sangio-Vincentelli,Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer Academic, 1984.
[4] R. Braytonet al., "MIS: A multiple level logic optimization system,"IEEE Trans. Comput.-Aided Design, vol. CAD-6, pp. 1062-1081, Nov. 1987.
[5] K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," inProc. 24th Design Automat. Conf., June 1987, pp. 341-347.
[6] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A directed search method for test generation using a concurrent fault simulator,"IEEE Trans. Comput.-Aided Design, vol. CAD-8, pp. 131-138, Feb. 1989.
[7] S. Mallela and S. Wu, "A sequential circuit test generation system," inProc. Inc. Test Conf., Philadelphia, PA, Nov. 1985, pp. 57-61.
[8] K. T. Cheng and V. D. Agrawal, "Concurrent test generation and design for testability," inProc. ISCAS, Portland, OR, May 1989, pp. 1935-1938.
[9] G. Hachtel, R. Jacoby, K. Keutzer, and C. Morrison, "On properties of algebraic transformations and the multifault testability of multilevel logic," inProc. Int. Conf. Comput.-Aided Design, Santa Clara, CA, Nov. 1989, pp. 422-425.
[10] K. Keutzer, private communication.
[11] Z. Kohavi,Switching and Finite Automata Theory, second edition. New York: McGraw-Hill, 1978.
[12] A. Miczo,Digital Logic Testing and Simulation. New York: Harper and Row, 1986.
[13] T. Villa and A. L. Sangiovanni-Vincentelli, "NOVA: State assignment of finite state machines for optimal two-level logic implementations," inProc. 26th Design Automat. Conf., June 1989, pp. 327-332.
[14] R. Lisanke, "Finite-state machine benchmark set,"Preliminary Benchmark Collection, Sept. 1987.

Index Terms:
initializability; sequential machine synthesis; finite-state machine; state encoding; synchronizing sequences; state assignment; logic optimization; gate-level analysis tools.; logic minimality; encoding; finite automata; logic design; logic testing; synchronisation.
Citation:
K.-T. Cheng, V.D. Agrawal, "Initializability Consideration in Sequential Machine Synthesis," IEEE Transactions on Computers, vol. 41, no. 3, pp. 374-379, March 1992, doi:10.1109/12.127453
Usage of this product signifies your acceptance of the Terms of Use.