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| K.-T. Cheng, V.D. Agrawal, "Initializability Consideration in Sequential Machine Synthesis," IEEE Transactions on Computers, vol. 41, no. 3, pp. 374-379, March, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/12.127453, author = {K.-T. Cheng and V.D. Agrawal}, title = {Initializability Consideration in Sequential Machine Synthesis}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {3}, issn = {0018-9340}, year = {1992}, pages = {374-379}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.127453}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Initializability Consideration in Sequential Machine Synthesis IS - 3 SN - 0018-9340 SP374 EP379 EPD - 374-379 A1 - K.-T. Cheng, A1 - V.D. Agrawal, PY - 1992 KW - initializability; sequential machine synthesis; finite-state machine; state encoding; synchronizing sequences; state assignment; logic optimization; gate-level analysis tools.; logic minimality; encoding; finite automata; logic design; logic testing; synchronisation. VL - 41 JA - IEEE Transactions on Computers ER - | |||
It is shown that a finite-state machine, whose state encoding is obtained only to reduce the amount of logic in the final implementation, may not be initializable by a logic simulator or a test generator even when the circuit is functionally initializable (i.e. has synchronizing sequences). A fault simulator or a sequential circuit test generator that assumes all memory elements initially to be in the unknown state will be totally ineffective for such a design. Proper consideration for initializability during state assignment and logic optimization can guarantee the success for gate-level analysis tools. The conditions for initializability of finite-state machines are derived, and an automatic state assignment algorithm for logic minimality and initializability is given. Experimental results show that, in most cases, this method does not require more hardware than the other methods that may produce an uninitializable design. A partial reset technique, recommended for machines without a synchronizing sequence, is also discussed.
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