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Issue No.03 - March (1992 vol.41)
pp: 366-369
ABSTRACT
<p>The wiring problem of providing a planar rectilinear wire connection between two sets of terminals which lie on two horizontal lines in the plane is called the river routing. The problem has been widely studied. It is normally studied in conjunction with design variable(s) optimization problem. The author studies this problem when there is at most one horizontal segment in each wire. Efficient optimal algorithms are given for the following design variables: offset, separation, area, and shortest total wire length. The tight upper bound on the separation is also given.</p>
INDEX TERMS
VLSI layout; optimal single jog river routing; wiring problem; planar rectilinear wire connection; design variable; optimization; optimal algorithms; offset; separation; area; shortest total wire length; tight upper bound; circuit layout CAD; VLSI.
CITATION
T.-C. Tuan, "On Optimal Single Jog River Routing (VLSI Layout)", IEEE Transactions on Computers, vol.41, no. 3, pp. 366-369, March 1992, doi:10.1109/12.127451
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