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On Optimal Single Jog River Routing (VLSI Layout)
March 1992 (vol. 41 no. 3)
pp. 366-369

The wiring problem of providing a planar rectilinear wire connection between two sets of terminals which lie on two horizontal lines in the plane is called the river routing. The problem has been widely studied. It is normally studied in conjunction with design variable(s) optimization problem. The author studies this problem when there is at most one horizontal segment in each wire. Efficient optimal algorithms are given for the following design variables: offset, separation, area, and shortest total wire length. The tight upper bound on the separation is also given.

[1] M. Blum, R. W. Floyd, V. R. Pratt, R. L. Rivest, and R. E. Tarjan, "Time bounds for selection,"J. Comput. Syst. Sci., vol. 7, no. 4, pp. 448-461, 1972.
[2] D. Dolev, K. Karplus, A. Siegel, A. Strong, and J. D. Ullman, "Optimal wiring between rectangles," inProc. 13th ACM STOC, 1981, pp. 312-317.
[3] E. Horowitz and S. Sahni,Fundamentals of Data Structures. Rockville, MD: Computer Science Press, 1983.
[4] C. E. Leiserson and R. Y. Pinter, "Optimal placement for river routing,"SIAM J. Comput., vol. 12, pp. 447-462, 1983.
[5] A. Mirzaian, "River routing in VLSI,"J. Comput. Syst. Sci., vol. 34, no. 1, pp. 43-54, 1987.
[6] A. Siegel and D. Dolev, "The separation for general single-layer wiring barriers," inProc. Carnegie-Mellon Conf. VLSI Syst. and Computat., Rockville, MD: Computer Science Press, 1981, pp. 143-152.
[7] A. Siegel and D. Dolev, "Some geometry for general river routing,"SIAM J. Comput., vol. 17, pp. 583-605, 1988.
[8] K. H. Teo and T. C. Tuan, "Performance analysis of greedy heuristic to find a minimum total-jogs layout for river routing,"Inform. Processing Lett., vol. 36, no. 4, pp. 167-170, Nov. 15, 1990.
[9] M. Truszynski, private communication, 1988.
[10] T. C. Tuan and S. L. Hakimi, "Single jog river routing," inProc. 25th Annu. Allerton Conf., 1987, pp. 375-374.
[11] T. C. Tuan and S. L. Hakimi, "River routing with a small number of jogs,"SIAM J. Disc. Math., vol. 3, no. 4, pp. 585-597, 1990.
[12] T. C. Tuan and K. H. Teo, "On river routing with minimum number of jogs,"IEEE Trans. Comput.-Aided Design, vol. 10, no. 2, pp. 270-273, 1991.
[13] J. D. Ullman,Computational Aspects of VLSI. Rockville, MD: Computer Science Press, 1984.

Index Terms:
VLSI layout; optimal single jog river routing; wiring problem; planar rectilinear wire connection; design variable; optimization; optimal algorithms; offset; separation; area; shortest total wire length; tight upper bound; circuit layout CAD; VLSI.
Citation:
T.-C. Tuan, "On Optimal Single Jog River Routing (VLSI Layout)," IEEE Transactions on Computers, vol. 41, no. 3, pp. 366-369, March 1992, doi:10.1109/12.127451
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