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PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness
March 1992 (vol. 41 no. 3)
pp. 361-366

The authors address the design and performance analysis of partial-multiple-bus interconnection networks. They are bus architectures that have evolved from the multiple-bus structure by dividing buses into groups and reducing bus connections. Their effect is to reduce cost and alleviate arbitration and drive requirements without degrading performance significantly. One such structure, called processor-oriented partial-multiple-bus (PPMB), is proposed. It serves as an alternative to the conventional structure called memory-oriented partial-multiple-bus (MPMB) and is aimed at higher system performance at less or equal system cost. It has been shown, both analytically and by simulation, that a substantial increase in system bandwidth (up to 20%) is achieved by the PPMB structure over the MPMB structure. With very large systems, the results also imply a significantly improved cost-effectiveness over the conventional multiple-bus architecture.

[1] D. P. Bhandarkar, "Analysis of memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-24, pp. 897-908, Sept. 1975.
[2] L. N. Bhuyan, "A combinatorial analysis of multibus multiprocessors," inProc. '84 Int. Conf. Parallel Processing, pp. 225-232.
[3] L. N. Bhuyan, "An analysis of processor-memory interconnection networks,"IEEE Trans. Comput., vol. C-34, pp. 279-283, Mar. 1985.
[4] C.R. Das and L.N. Bhuyan, "Bandwidth Availability of Multiple-bus Multiprocessors,"IEEE Trans. Computers, Vol C-34, Oct. 1985, pp. 918-926.
[5] H. Jiang, "Partial-multiple-bus computer structures with improved cost-effectiveness," M.A.Sc. Thesis, Dep. Elec. Eng., Univ. of Toronto, Jan. 1987.
[6] T. Langet al., "Bandwidth of crossbar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, pp. 1227-1233, Dec. 1982.
[7] T. Lang and M. Valero, "M-users B-servers arbiter for multiple-buses multiprocessors,"Microprocessing and Microprogramming, North-Holland Publishing Company, 10, 1982, pp. 11-18.
[8] Q. Yang, "Communication performance in multiple-bus systems," M.A.Sc. Thesis, Dep. Elec. Eng., Univ. of Toronto, 1985.
[9] D. W. L. Yen, J. H. Patel, and E. S. Davidson, "Memory interference in synchronous multiprocessor systems,"IEEE Trans. Comput., vol. C-31, pp. 1116-1121, Nov. 1982.

Index Terms:
PPMB; partial-multiple-bus multiprocessor architecture; cost-effectiveness; design; performance analysis; interconnection networks; arbitration; processor-oriented partial-multiple-bus; memory-oriented partial-multiple-bus; simulation; system bandwidth; computer architecture; multiprocessor interconnection networks; performance evaluation.
Citation:
H. Jiang, K.C. Smith, "PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness," IEEE Transactions on Computers, vol. 41, no. 3, pp. 361-366, March 1992, doi:10.1109/12.127450
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