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Systolic Super Summation with Reduced Hardware
March 1992 (vol. 41 no. 3)
pp. 339-342

A systolic super summer is a cellular apparatus for summing floating-point numbers. The apparatus receives floating-point summands, converting them to fixed-point within a sieve-like cellular array. The emerging fixed-point numbers are summed in a pipelined array of long accumulators. An improved design is presented for the summer's sieve. Although the new sieve is structurally simpler and uses less hardware, the throughput per unit area is the same as that for the previously designed sieve. The new sieve's architectural regularity makes it ideal for implementation in VLSI circuit technology.

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Index Terms:
systolic super summation; reduced hardware; cellular apparatus; floating-point numbers; sieve-like cellular array; fixed-point numbers; pipelined array; architectural regularity; VLSI circuit technology; digital arithmetic; systolic arrays.
Citation:
P.R. Cappello, W.L. Miranker, "Systolic Super Summation with Reduced Hardware," IEEE Transactions on Computers, vol. 41, no. 3, pp. 339-342, March 1992, doi:10.1109/12.127445
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