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| M.-C. Chiang, G.S. Sohi, "Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment," IEEE Transactions on Computers, vol. 41, no. 3, pp. 297-317, March, 1992. | |||
| BibTex | x | ||
| @article{ 10.1109/12.127442, author = {M.-C. Chiang and G.S. Sohi}, title = {Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {3}, issn = {0018-9340}, year = {1992}, pages = {297-317}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.127442}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
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| TY - JOUR JO - IEEE Transactions on Computers TI - Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment IS - 3 SN - 0018-9340 SP297 EP317 EPD - 297-317 A1 - M.-C. Chiang, A1 - G.S. Sohi, PY - 1992 KW - shared bus multiprocessors; throughput-oriented environment; performance; overall throughput; design choices; mean value analysis analytical models; trace-driven simulation analysis; cache block sizes; cache set associativity; multiprocessor throughput; digital simulation; multiprocessing systems; performance evaluation. VL - 41 JA - IEEE Transactions on Computers ER - | |||
The authors consider the evaluation of design choices in multiprocessors with a single, shared bus interconnect operating in an environment in which each task is being executed on a single processor and the performance of the multiprocessor is measured by its overall throughput. To evaluate design choices, they develop mean value analysis analytical models and validate the models by comparing their results against the results of a trace-driven simulation analysis for 5376 multiprocessor configurations. The trace-driven simulation uses actual programs and simulates their execution in a throughput-oriented environment. It is found that: (1) cache block sizes that yield the best performance in a multiprocessor differ from the block sizes that yield the best uniprocessor performance metrics, (2) a larger cache set associativity might be warranted in a multiprocessor even though it might not be warranted in a uniprocessor, (3) a split transaction, pipelined bus yields much higher multiprocessor throughput than a circuit switched bus, especially for larger main memory latencies, and (4) increasing the bus width appears to be an effective way of improving multiprocessor throughput.
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