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A Multiple Seed Linear Feedback Shift Register
February 1992 (vol. 41 no. 2)
pp. 250-252

The authors describe a design of an LFSR (linear feedback shift register) that can easily accommodate a change-of-seeds feature. This new LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change of seeds option. The change of seeds is fast since it is accomplished by a pair of clock pulses rather than by long scan operations.

[1] Y. Nozuyamaet al., "Design for testability of a 32-bit microprocessor, the TX1," inProc. 1988 Int. Test Conf., 1988, pp. 172-182.
[2] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.
[3] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability,"J. Design Automat. Fault-Tolerant Comput., vol. 2, no. 2, pp. 165-178, 1978.
[4] R. David, "Testing by feedback shift register,"IEEE Trans. Comput., vol. C-29, pp. 668-673, July 1980.

Index Terms:
multiple seed linear feedback shift register; LFSR; change-of-seeds; clock pulses; built-in self test; feedback; shift registers.
Citation:
J. Savir, W.H. McAnney, "A Multiple Seed Linear Feedback Shift Register," IEEE Transactions on Computers, vol. 41, no. 2, pp. 250-252, Feb. 1992, doi:10.1109/12.123404
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