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Four State Asynchronous Architectures
February 1992 (vol. 41 no. 2)
pp. 129-142

An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block.

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Index Terms:
four state asynchronous architectures; asynchronous wavefront array; throughput; design complexity; reliability; one-dimensional multipliers; two-dimensional sorter; asynchronous sequential logic; many-valued logics; sequential circuits.
Citation:
A.J. McAuley, "Four State Asynchronous Architectures," IEEE Transactions on Computers, vol. 41, no. 2, pp. 129-142, Feb. 1992, doi:10.1109/12.123391
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