Issue No.01 - January (1992 vol.41)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.123383
<p>The authors deal with reconfiguration of a rectangular array of processors arranged as an N*N mesh, and a complete binary tree of N processors. They present new reconfiguration techniques that are modifications of the Diogenes approach proposed earlier by A.L. Rosenberg et al. (1983). These techniques reduce the overheads incurred in the earlier Diogenes schemes. Some of the previous approaches to the problem are summarized. Two schemes are presented for reconfiguring rectangular arrays and a scheme for reconfiguring trees. For the analysis of the different schemes presented, it is assumed that a processor has a square layout. These schemes are analyzed and their performance results are presented.</p>
reconfiguration strategies; VLSI processor arrays; trees; Diogenes approach; complete binary tree; rectangular arrays; circuit layout CAD; fault tolerant computing; trees (mathematics); VLSI.
K.P. Bekhale, P. Banerjee, "Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach", IEEE Transactions on Computers, vol.41, no. 1, pp. 83-96, January 1992, doi:10.1109/12.123383