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Issue No.01 - January (1992 vol.41)
pp: 68-82
ABSTRACT
<p>Existing approaches to implement state saving are not appropriate for large Time Warp programs. The authors propose a component called the rollback chip (RBC) that efficiently implements state saving. Such a component could be used in a programmable, special purpose parallel discrete event simulation engine based on Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented that show that the rollback chip can virtually eliminate the state saving and rollback overheads that plague current software implementations of Time Warp.</p>
INDEX TERMS
rollback chip; special purpose hardware; Time Warp; parallel discrete event simulation engine; state saving; software implementations; discrete event simulation; microprocessor chips; parallel architectures.
CITATION
R.M. Fujimoto, J.-J. Tsai, G.C. Gopalakrishnan, "Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp", IEEE Transactions on Computers, vol.41, no. 1, pp. 68-82, January 1992, doi:10.1109/12.123382
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