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Implementing Sequential Machines as Self-Timed Circuits
January 1992 (vol. 41 no. 1)
pp. 12-17

A self-timed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of self-timed combinational logic and a self-timed master-slave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of self-timed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are double-rail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches.

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Index Terms:
temporal behaviour constraints; self-timed circuits; finite state machine; combinational logic; master-slave register; automatic compiler; state table; combinatorial mathematics; finite automata; logic design; sequential machines.
Citation:
I. David, R. Ginosar, M. Yoeli, "Implementing Sequential Machines as Self-Timed Circuits," IEEE Transactions on Computers, vol. 41, no. 1, pp. 12-17, Jan. 1992, doi:10.1109/12.123378
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