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I. David, R. Ginosar, M. Yoeli, "Implementing Sequential Machines as SelfTimed Circuits," IEEE Transactions on Computers, vol. 41, no. 1, pp. 1217, January, 1992.  
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@article{ 10.1109/12.123378, author = {I. David and R. Ginosar and M. Yoeli}, title = {Implementing Sequential Machines as SelfTimed Circuits}, journal ={IEEE Transactions on Computers}, volume = {41}, number = {1}, issn = {00189340}, year = {1992}, pages = {1217}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.123378}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Implementing Sequential Machines as SelfTimed Circuits IS  1 SN  00189340 SP12 EP17 EPD  1217 A1  I. David, A1  R. Ginosar, A1  M. Yoeli, PY  1992 KW  temporal behaviour constraints; selftimed circuits; finite state machine; combinational logic; masterslave register; automatic compiler; state table; combinatorial mathematics; finite automata; logic design; sequential machines. VL  41 JA  IEEE Transactions on Computers ER   
A selftimed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of selftimed combinational logic and a selftimed masterslave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of selftimed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are doublerail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches.
[1] T. S. Anantharaman, "A delay insensitive regular expression recognizer,"IEEE VLSI Tech. Bull., vol. 1, no. 2, Sept. 1986.
[2] T. A. Chu, "Synthesis of selftimed VLSI circuits from graphtheoretic specifications," Ph.D. dissetation, Massachusetts Institute of Technology, 1987.
[3] I. David, R. Ginosar, and M. Yoeli, "An efficient implementation of Boolean functions as selftimed circuits,"IEEE Trans. Comput., this issue, pp. 211.
[4] I. David, R. Ginosar, and M. Yoeli, "Implementing sequential machines as selftimed circuits," Tech. Rep. 692, Dep. Elec. Eng., Technion, Nov. 1988.
[5] J. C. Ebergen, "Translating programs into delayinsensitive circuits," Ph.D. dissertation, Eindhoven Univ. of Technology, 1987.
[6] Z. Kohavi,Switching and Finite Automata Theory, second edition. New York: McGrawHill, 1978.
[7] A. J. Martin, "Compiling communicating processes into delay insensitive VLSI circuits,"Distributed Comput., vol. 1, no. 3, pp. 226234, 1986.
[8] A. J. Martin, "Programming in VLSI: From communicating processes to delayinsensitive circuits," CaltechCSTR891, Dep. Comput. Sci., California Institute of Technology, 1989.
[9] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: AddisonWesley, 1980, pp. 150152.
[10] C. E. Molnar, T. P. Fan, and F. U. Rosenberger, "Synthesis of delayinsensitive modules," inProc. 1985 Chapel Hill Conf. VLSI, Chapel Hill, NC, May 1527, 1985, pp. 6786.
[11] M. Rem, "Concurrent computations and VLSI circuits," inControl Flow and Data Flow; Concepts of Distributed Computing, M. Broy Ed. Berlin, Germany: SpringerVerlag, 1985, pp. 399437.
[12] C. L. Seitz, "System timing," inIntroduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: AddisonWesley, 1980, pp, 218262.
[13] J. L. A., Van de Snepscheut,Trace Theory and VLSI Design, LNCS 200, 1985.