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W.M. Lin, V.K. Prasanna, K.W. Przytula, "Algorithmic mapping of neural network Models onto Parallel SIMD Machines," IEEE Transactions on Computers, vol. 40, no. 12, pp. 13901401, December, 1991.  
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@article{ 10.1109/12.106224, author = {W.M. Lin and V.K. Prasanna and K.W. Przytula}, title = {Algorithmic mapping of neural network Models onto Parallel SIMD Machines}, journal ={IEEE Transactions on Computers}, volume = {40}, number = {12}, issn = {00189340}, year = {1991}, pages = {13901401}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.106224}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Algorithmic mapping of neural network Models onto Parallel SIMD Machines IS  12 SN  00189340 SP1390 EP1401 EPD  13901401 A1  W.M. Lin, A1  V.K. Prasanna, A1  K.W. Przytula, PY  1991 KW  algorithmic mapping; matrix operations; neural network models; parallel SIMD machines; programmable massively parallel computers; graph theoretic approach; vector operations; processor array; nonzero synaptic weights; data transfers; neurons; routing algorithm; graph theory; neural nets; parallel processing. VL  40 JA  IEEE Transactions on Computers ER   
Implementations of neural networks on programmable massively parallel computers are addressed. The methods are based on a graph theoretic approach and are applicable to a large class of networks in which the computations can be described by means of matrix and vector operations. A detailed characterization of the target machine is provided. Two mappings are presented. The first is designed for a processor array consisting of a very large number of small processing units. The neurons and the nonzero synaptic weights are assigned to the processors in a predetermined order, one per processor. The data transfers between processors containing neurons and weights are implemented using a novel routing algorithm. The second mapping is designed for the data array of size N*N and a smaller processor array of size P*P, P>>N, i.e., it addresses the partitioned case. These mappings are applicable to most of the meshconnected singleinstructionmultipledata (SIMD) machines.
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